[PATCH][AARCH64]Use shl for vec_shr_<mode> rtx pattern.

[Renlin Li]

Hi all,

unsigned shift left dosen't support immediate shift. Previouly, gcc will 
generate asm instruction like this: "ushl d1, d0, 32", which is not a 
legal insn and will be rejected by assembler. This patch change the use 
of ushl in vec_shr_<mode> into shl.

A test case is added, and it passes on both aarch64-none-elf and 
aarch64_be-none-elf tool-chain.

Okay to commit?

Regards,
Renlin Li

gcc/ChangeLog:

2015-04-28  Renlin Li  <renlin.li@arm.com>

     * config/aarch64/aarch64-simd.md (vec_shr_<mode>): Use shl.

gcc/testsuite/ChangeLog:

2015-04-28  Renlin Li  <renlin.li@arm.com>
                     Alan Lawrence  <alan.lawrence@arm.com>

     * gcc.target/aarch64/vect-reduc-or_1.c: New.
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