[wwwdocs] Update changes.html with Intel MPX and Pointer Bounds Checker

[Ilya Enkovich]

Hi,

This adds Pointer Bounds Checker and MPX support to GCC 5 changes. Is it OK?

Thanks,
Ilya
--

--- changes.html	2015-04-09 12:18:47.672300000 +0300
+++ changes.html	2015-04-09 12:58:23.677983000 +0300
@@ -158,20 +158,29 @@
       <li><code>-fsanitize=alignment</code>: enable alignment checking, detect
 	  various misaligned objects;</li>
       <li><code>-fsanitize=object-size</code>: enable object size checking, detect
 	  various out-of-bounds accesses.</li>
       <li><code>-fsanitize=vptr</code>: enable checking of C++ member function
 	  calls, member accesses and some conversions between pointers to base
 	  and derived classes, detect if the referenced object does not have
 	  the correct dynamic type.</li>
     </ul>
     </li>
+    <li>Pointer Bounds Checker, a bounds violation detector, has been added and
+      can be enabled via <code>-fcheck-pointer-bounds</code>.  Memory accesses are
+      instrumented with runtime checks of used pointers against their bounds to
+      detect pointer bounds violations (overflows).  The Pointer Bounds Checker
+      is available on IA-32/x86-64 GNU/Linux target with a new ISA extension
+      Intel MPX support.  See Pointer Bounds Checker
+      <a href="https://gcc.gnu.org/wiki/Intel%20MPX%20support%20in%20the%20GCC%20compiler">
+	Wiki page</a> for more details.
+    </li>
   </ul>
 
 <h2 id="languages">New Languages and Language specific improvements</h2>
   <ul>
     <li id="offload"><a href="http://www.openmp.org/mp-documents/OpenMP4.0.0.pdf">
       OpenMP 4.0 specification</a> offloading features are now supported by the C, C++,
 	and Fortran compilers. Generic changes:
 	<ul>
 	  <li>Infrastructure (suitable for any vendor).</li>
 	  <li>Testsuite which covers offloading from the
@@ -676,20 +685,28 @@
 	AVX-512{BW,DQ,VL,IFMA,VBMI}</a> of Intel's CPU
 	codenamed Skylake Server was added to GCC.  That includes inline
 	assembly support, new intrinsics, and basic autovectorization.  These
 	new AVX-512 extensions are available via
 	the following GCC switches: AVX-512 Vector Length EVEX feature:
 	<code>-mavx512vl</code>, AVX-512 Byte and Word instructions:
 	<code>-mavx512bw</code>, AVX-512 Dword and Qword instructions:
 	<code>-mavx512dq</code>, AVX-512 FMA-52 instructions:
 	<code>-mavx512ifma</code> and for AVX-512 Vector Bit Manipulation
 	Instructions: <code>-mavx512vbmi</code>.</li>
+	<li>New ISA extensions support
+	<a href="https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf">
+	Intel MPX</a> was added to GCC.  New extension is available via <code>-mmpx</code>
+	compiler switch.  Intel MPX is a set of processor features which,
+	with compiler, runtime library and OS support, brings increased robustness to
+	software by runtime checking pointer references against their bounds.
+	In GCC Intel MPX is supported by Pointer Bounds Checker and libmpx runtime
+	libraries.</li>
 	<li>The new <code>-mrecord-mcount</code> option for <code>-pg</code>
 	generates a Linux kernel style table of pointers to mcount or
 	__fentry__ calls at the beginning of functions. The new
 	<code>-mnop-mcount</code> option in addition also generates nops in
 	place of the __fentry__ or mcount call, so that a call per function
 	can be later patched in. This can be used for low overhead tracing or
 	hot code patching.</li>
 	<li>The new <code>-malign-data</code> option controls how
 	GCC aligns variables.  <code>-malign-data=compat</code> uses
 	increased alignment compatible with GCC 4.8 and earlier,