[PATCH X86, PR62128] Rotate pattern for AVX2

Evgeny Stupachenko evstupac@gmail.com
Tue Sep 30 22:13:00 GMT 2014


expand_vselect for some reason ignores the expander.
Does it work with expanders?
The comment talks about insn only:
/* Construct (set target (vec_select op0 (parallel perm))) and
   return true if that's a valid instruction in the active ISA.  */

On Tue, Sep 30, 2014 at 10:21 PM, Uros Bizjak <ubizjak@gmail.com> wrote:
> On Tue, Sep 30, 2014 at 8:08 PM, Uros Bizjak <ubizjak@gmail.com> wrote:
>> On Tue, Sep 30, 2014 at 7:06 PM, Uros Bizjak <ubizjak@gmail.com> wrote:
>>> On Tue, Sep 30, 2014 at 6:47 PM, Evgeny Stupachenko <evstupac@gmail.com> wrote:
>>>
>>>> Patch resubmitted from https://gcc.gnu.org/ml/gcc-patches/2014-09/msg01400.html
>>>>
>>>> The patch fix PR62128 and  "gcc.target/i386/pr52252-atom.c" in
>>>> core-avx2 make check.
>>>> The test in pr62128 is exactly TEST 22 from
>>>> gcc.dg/torture/vshuf-v32qi.c. It will check if the pattern is correct
>>>> or not.
>>>> The patch developed similar to define_insn_and_split
>>>> "*avx_vperm_broadcast_<mode>".
>>>> The patch passed x86 bootstrap and make check (+2 new passes for
>>>> -march=core-avx2).
>>>> Is it ok?
>>
>> Please try following (totally untested) expander:
>
> As usual, the wrong version was pasted. This should read:
>
> --cut here--
> (define_expand "avx2_rotate<mode>_perm"
>   [(set (match_operand:V_256 0 "register_operand")
>       (vec_select:V_256
>     (match_operand:V_256 1 "register_operand")
>     (match_parallel 2 "palignr_operand"
>       [(match_operand 3 "const_int_operand" "n")])))]
>   "TARGET_AVX2"
> {
>   int shift = INTVAL (operands[3]) * <ssescalarsize>;
>   rtx insn;
>
>   rtx op1 = gen_lowpart (V4DImode, operands[1]);
>   rtx t2 = gen_reg_rtx (V4DImode);
>
>   emit_insn (gen_avx2_permv2ti (t2, op1, op1, GEN_INT (33)));
>
>   op0 = gen_lowpart (V2TImode, operands[0]);
>   op1 = gen_lowpart (V2TImode, operands[1]);
>   t2 = gen_lowpart (V2TImode, t2);
>
>   if (shift < GET_MODE_SIZE (TImode))
>     insn = gen_avx2_palignrv2ti (op0, t2, op1, GEN_INT (shift)));
>   else
>     insn = gen_avx2_palignrv2ti (op0, op1, t2, GEN_INT (shift - 16)));
>
>   emit_insn (insn);
>   DONE;
> }
> --cut here--
>
> Uros.



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