[PATCH 0/5] Fix handling of word subregs of wide registers

Richard Sandiford richard.sandiford@arm.com
Mon Sep 22 11:29:00 GMT 2014


Andrew Pinski <pinskia@gmail.com> writes:
> On Thu, Sep 18, 2014 at 3:07 AM, Richard Sandiford
> <richard.sandiford@arm.com> wrote:
>> This series is a cleaned-up version of:
>>
>>     https://gcc.gnu.org/ml/gcc/2014-03/msg00163.html
>>
>> The underlying problem is that the semantics of subregs depend on the
>> word size.  You can't have a subreg for byte 2 of a 4-byte word, say,
>> but you can have a subreg for word 2 of a 4-word value (as well as lowpart
>> subregs of that word, etc.).  This causes problems when an architecture has
>> wider-than-word registers, since the addressability of a word can then depend
>> on which register class is used.
>>
>> The register allocators need to fix up cases where a subreg turns out to
>> be invalid for a particular class.  This is really an extension of what
>> we need to do for CANNOT_CHANGE_MODE_CLASS.
>>
>> Tested on x86_64-linux-gnu, powerpc64-linux-gnu and aarch64_be-elf.
>
>
> This sounds like something which should be tested on spu as it is the
> main target that I can think of which has wider-than-word registers
> and that has had issues with subreg.  I can't remember if the
> simulator for SPU is free (as in beer) and would run on anything
> besides PowerPC.  It has been more than 4 years since I looked into
> the spu back-end also.

Well, AArch64 and x86_64 should be good enough targets for testing
the patch.  In the AArch64 case the bug was holding up other big-endian
fixes, in the x86_64 case it led to a workaround in C_C_M_C.

Thanks,
Richard



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