[PATCH] Improve prepare_shrink_wrap to sink more instructions

[Jeff Law]

On 09/15/14 08:33, Jiong Wang wrote:
>
> Jeff,
>
>   thanks, I partially understand your meaning here.
>
>    take the function "ira_implicitly_set_insn_hard_regs" in ira-lives.c
> for example,
>
>    when generating address rtl, gcc will automatically generate "const"
> operator to prefix
>    the address expression, like the following. so a simple CONSTANT_P
> check is enough in
>    case there is no embedded register.
>
>    (insn 309 310 308 3 (set (reg:DI 44 r15 [orig:94 ivtmp.674 ] [94])
>          (const:DI (plus:DI (symbol_ref:DI ("recog_data") [flags 0x40]
> <var_decl 0x2b2c2ff91510 recog_data>)
>                  (const_int 480 [0x1e0])))) -1
>
>
>    but for architecture like aarch64, the following instruction
> sequences to forming address
>    may be generated
>
> (insn 73 14 74 4 (set (reg/f:DI 20 x20 [99])
>          (high:DI (symbol_ref:DI ("global_a") [flags 0xc0]  <var_decl
> 0x7ff755a60900 stats>))) 35 {*movdi_aarch64}
>       (expr_list:REG_EQUIV (high:DI (symbol_ref:DI ("global_a") [flags
> 0xc0]  <var_decl 0x7ff755a60900 stats>))
>          (nil)))
>
> (insn 17 30 25 5 (set (reg/f:DI 4 x4 [83])
>          (lo_sum:DI (reg/f:DI 20 x20 [99])
>              (symbol_ref:DI ("global_a") [flags 0xc0]  <var_decl
> 0x7ff755a60900 stats>))) {add_losym_di}
>       (expr_list:REG_EQUIV (symbol_ref:DI ("global_a") [flags 0xc0]
> <var_decl 0x7ff755a60900 stats>)
>          (nil)))
>
>   while CONSTANT_P could not catch the latter lo_sum case, as the
> RTX_CLASS of lo_sum is RTX_OBJ not RTX_CONST_OBJ,
Hmm, it's been ~15 years since I regularly worked on a target that uses 
HIGH/LO_SUM, I thought we wrapped the LO_SUM expression inside a CONST 
as well, but reading the docs for CONST, that clearly isn't the case.

Sorry for that.  Can you (re) send your current patch for this for review?

Jeff