[PATCH], Fix constraints on VSX Fma, Fix, and Reduce options

David Edelsohn dje.gcc@gmail.com
Wed Sep 10 20:42:00 GMT 2014

On Wed, Sep 10, 2014 at 4:16 PM, Michael Meissner
<meissner@linux.vnet.ibm.com> wrote:
> In doing work on improving power8 fusion support, I noticed that in several of
> the patterns (vector fused multiply-add, optimization of float (fix (x)), and
> vector reduction), I used the "ws" constraint which is the constraint for
> scalar double precision floating point (currently FLOAT_REGS) in cases where
> the operand is a vector, where we should use "wd" (preferred constraint for
> V2DF), "wf" (preferred constraint for V4SF) or even "wa" (any VSX register).
> This means the register allocator might generate extra code due to preferring
> the traditional floating point registers.
> I was curious about the code generation changes, so I built power8 versions of
> the Spec 2006 benchmark suite, and compared the number of instructions
> generated, using the same options.  Most of the floating point benchmarks had
> some changes in code generation, including fewer scalar floating loads/stores
> (where the RA picked a traditional scalar register, which meant elsewere a
> scalar was spilled to the stack), and different encodings of the FMA
> instructions.
> I did a run of the FP spec benchmarks on a big endian power8 system.  There
> were no regressions that were significant, and the cactusADM benchmark sped up
> by 2%.
> I did a bootstrap/make check comparison, and there were no regressions.  Is it
> ok to install in trunk and the active PowerPC branches?

Needs a ChangeLog.


thanks, David

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