[PATCH ARM]Use stricter constraint for pattern arm_movqi_insn to avoid constant pool

Bin Cheng bin.cheng@arm.com
Thu Sep 4 05:33:00 GMT 2014


Hi,
This patch is to fix a potential bug in arm pattern "arm_movqi_insn".

For the pattern,
(define_insn "*arm_movqi_insn"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,l,r,l,Uu,r,m")
	(match_operand:QI 1 "general_operand" "r,r,I,Py,K,Uu,l,m,r"))]
  "TARGET_32BIT
   && (   register_operand (operands[0], QImode)
       || register_operand (operands[1], QImode))"
  "@
   mov%?\\t%0, %1
   mov%?\\t%0, %1
   mov%?\\t%0, %1
   mov%?\\t%0, %1
   mvn%?\\t%0, #%B1
   ldr%(b%)\\t%0, %1
   str%(b%)\\t%1, %0
   ldr%(b%)\\t%0, %1
   str%(b%)\\t%1, %0"
  [(set_attr "type"
"mov_reg,mov_reg,mov_imm,mov_imm,mvn_imm,load1,store1,load1,store1")
   (set_attr "predicable" "yes")
   (set_attr "predicable_short_it" "yes,yes,yes,no,no,no,no,no,no")
   (set_attr "arch" "t2,any,any,t2,any,t2,t2,any,any")
   (set_attr "length" "2,4,4,2,4,2,2,4,4")]
)

Both predicate "general_operand" and constraint "m" of the 2nd operand
support load from constant pool.  Problem is both attribute pool_range and
neg_pool_range are default to 0 because we don't set it explicitly.  When
GCC comes to situation that it generates load from constant pool for this
pattern, function push_minipool_fix runs into assertion failure.

This patch uses stricter constraint "Uh" just like r212303.  This patch is
necessary for inlining memset calls on ARM target.

It passes tests on
arm-none-eabi/arm-none-linux-gnueabi/arm-none-linux-gnueabihf with different
test variants.  It also passes bootstrap and glibc build on
arm-none-linux-gnueabihf.  Is it OK?

Thanks,
bin

2014-09-04  Bin Cheng  <bin.cheng@arm.com>

	* config/arm/arm.md (arm_movqi_insn): Use Uh instead of m
constraint.
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