[PATCH 3/X, i386, PR54232] Enable EBX for x86 in 32bits PIC code
Uros Bizjak
ubizjak@gmail.com
Mon Oct 13 16:22:00 GMT 2014
On Mon, Oct 13, 2014 at 5:17 PM, Evgeny Stupachenko <evstupac@gmail.com> wrote:
> Patch updated with the comment:
>
> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> index 2a64d2d..5fd6a82 100644
> --- a/gcc/config/i386/i386.c
> +++ b/gcc/config/i386/i386.c
> @@ -12455,9 +12455,18 @@ ix86_address_cost (rtx x, enum machine_mode,
> addr_space_t, bool)
> || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
> cost++;
>
> + /* When address base or index is "pic_offset_table_rtx" we don't increase
> + address cost. When a memop with "pic_offset_table_rtx" is not invariant
> + itself it most likely means that base or index is not invariant.
> + Therefore only "pic_offset_table_rtx" could be hoisted out, which is not
> + profitable for x86. */
> if (parts.base
> + && (!pic_offset_table_rtx
> + || REGNO (pic_offset_table_rtx) != REGNO(parts.base))
> && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
> && parts.index
> + && (!pic_offset_table_rtx
> + || REGNO (pic_offset_table_rtx) != REGNO(parts.index))
> && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
> && parts.base != parts.index)
> cost++;
LGTM.
OK.
Thanks,
Uros.
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