[PATCH 2/9] rs6000: New type attribute value "halfmul"
Segher Boessenkool
segher@kernel.crashing.org
Fri May 23 06:13:00 GMT 2014
This is for the legacy integer multiply-accumulate instructions.
Quite a mouthful, and "mulhw" is also a terrible name since we already
have a machine instruction called exactly that. Hence "halfmul".
Also fixes the titan automaton description for this.
2014-05-22 Segher Boessenkool <segher@kernel.crashing.org>
gcc/
* config/rs6000/rs6000.md (type): Add new value "halfmul".
(*macchwc, *macchw, *macchwuc, *macchwu, *machhwc, *machhw,
*machhwuc, *machhwu, *maclhwc, *maclhw, *maclhwuc, *maclhwu,
*nmacchwc, *nmacchw, *nmachhwc, *nmachhw, *nmaclhwc, *nmaclhw,
*mulchwc, *mulchw, *mulchwuc, *mulchwu, *mulhhwc, *mulhhw,
*mulhhwuc, *mulhhwu, *mullhwc, *mullhw, *mullhwuc, *mullhwu):
Use it.
* config/rs6000/40x.md (ppc405-imul3): Add type halfmul.
* config/rs6000/440.md (ppc440-imul2): Add type halfmul.
* config/rs6000/476.md (ppc476-imul): Add type halfmul.
* config/rs6000/titan.md: Delete nonsensical comment.
(titan_imul): Add type imul3.
(titan_mulhw): Remove type imul3; add type halfmul.
---
gcc/config/rs6000/40x.md | 2 +-
gcc/config/rs6000/440.md | 2 +-
gcc/config/rs6000/476.md | 2 +-
gcc/config/rs6000/rs6000.md | 62 ++++++++++++++++++++++-----------------------
gcc/config/rs6000/titan.md | 8 ++----
5 files changed, 36 insertions(+), 40 deletions(-)
diff --git a/gcc/config/rs6000/40x.md b/gcc/config/rs6000/40x.md
index ed236a4..5510767 100644
--- a/gcc/config/rs6000/40x.md
+++ b/gcc/config/rs6000/40x.md
@@ -73,7 +73,7 @@ (define_insn_reservation "ppc405-imul2" 3
"iu_40x*2")
(define_insn_reservation "ppc405-imul3" 2
- (and (eq_attr "type" "imul3")
+ (and (eq_attr "type" "imul3,halfmul")
(eq_attr "cpu" "ppc405"))
"iu_40x")
diff --git a/gcc/config/rs6000/440.md b/gcc/config/rs6000/440.md
index 2dcc58d..df3a3b5 100644
--- a/gcc/config/rs6000/440.md
+++ b/gcc/config/rs6000/440.md
@@ -76,7 +76,7 @@ (define_insn_reservation "ppc440-imul" 3
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-imul2" 2
- (and (eq_attr "type" "imul2,imul3")
+ (and (eq_attr "type" "imul2,imul3,halfmul")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
diff --git a/gcc/config/rs6000/476.md b/gcc/config/rs6000/476.md
index 8b4e65f..acfe063 100644
--- a/gcc/config/rs6000/476.md
+++ b/gcc/config/rs6000/476.md
@@ -82,7 +82,7 @@ (define_insn_reservation "ppc476-compare" 4
ppc476_i_pipe")
(define_insn_reservation "ppc476-imul" 4
- (and (eq_attr "type" "imul,imul_compare,imul2,imul3")
+ (and (eq_attr "type" "imul,imul_compare,imul2,imul3,halfmul")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe")
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 667aac1..3e9686e 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -160,7 +160,7 @@ (define_c_enum "unspecv"
(define_attr "type"
"integer,two,three,
shift,var_shift_rotate,insert_word,insert_dword,
- imul,imul2,imul3,lmul,idiv,ldiv,
+ imul,imul2,imul3,lmul,halfmul,idiv,ldiv,
exts,cntlz,popcnt,isel,
load,store,fpload,fpstore,vecload,vecstore,
cmp,
@@ -1248,7 +1248,7 @@ (define_insn "*macchwc"
(match_dup 4)))]
"TARGET_MULHW"
"macchw. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*macchw"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1260,7 +1260,7 @@ (define_insn "*macchw"
(match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW"
"macchw %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*macchwuc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1280,7 +1280,7 @@ (define_insn "*macchwuc"
(match_dup 4)))]
"TARGET_MULHW"
"macchwu. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*macchwu"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1292,7 +1292,7 @@ (define_insn "*macchwu"
(match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW"
"macchwu %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*machhwc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1314,7 +1314,7 @@ (define_insn "*machhwc"
(match_dup 4)))]
"TARGET_MULHW"
"machhw. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*machhw"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1327,7 +1327,7 @@ (define_insn "*machhw"
(match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW"
"machhw %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*machhwuc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1349,7 +1349,7 @@ (define_insn "*machhwuc"
(match_dup 4)))]
"TARGET_MULHW"
"machhwu. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*machhwu"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1362,7 +1362,7 @@ (define_insn "*machhwu"
(match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW"
"machhwu %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*maclhwc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1380,7 +1380,7 @@ (define_insn "*maclhwc"
(match_dup 4)))]
"TARGET_MULHW"
"maclhw. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*maclhw"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1391,7 +1391,7 @@ (define_insn "*maclhw"
(match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW"
"maclhw %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*maclhwuc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1409,7 +1409,7 @@ (define_insn "*maclhwuc"
(match_dup 4)))]
"TARGET_MULHW"
"maclhwu. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*maclhwu"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1420,7 +1420,7 @@ (define_insn "*maclhwu"
(match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW"
"maclhwu %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*nmacchwc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1440,7 +1440,7 @@ (define_insn "*nmacchwc"
(match_dup 1)))))]
"TARGET_MULHW"
"nmacchw. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*nmacchw"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1452,7 +1452,7 @@ (define_insn "*nmacchw"
(match_operand:HI 1 "gpc_reg_operand" "r")))))]
"TARGET_MULHW"
"nmacchw %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*nmachhwc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1474,7 +1474,7 @@ (define_insn "*nmachhwc"
(const_int 16)))))]
"TARGET_MULHW"
"nmachhw. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*nmachhw"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1487,7 +1487,7 @@ (define_insn "*nmachhw"
(const_int 16)))))]
"TARGET_MULHW"
"nmachhw %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*nmaclhwc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1505,7 +1505,7 @@ (define_insn "*nmaclhwc"
(match_dup 2)))))]
"TARGET_MULHW"
"nmaclhw. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*nmaclhw"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1516,7 +1516,7 @@ (define_insn "*nmaclhw"
(match_operand:HI 2 "gpc_reg_operand" "r")))))]
"TARGET_MULHW"
"nmaclhw %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mulchwc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1534,7 +1534,7 @@ (define_insn "*mulchwc"
(match_dup 1))))]
"TARGET_MULHW"
"mulchw. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mulchw"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1545,7 +1545,7 @@ (define_insn "*mulchw"
(match_operand:HI 1 "gpc_reg_operand" "r"))))]
"TARGET_MULHW"
"mulchw %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mulchwuc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1563,7 +1563,7 @@ (define_insn "*mulchwuc"
(match_dup 1))))]
"TARGET_MULHW"
"mulchwu. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mulchwu"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1574,7 +1574,7 @@ (define_insn "*mulchwu"
(match_operand:HI 1 "gpc_reg_operand" "r"))))]
"TARGET_MULHW"
"mulchwu %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mulhhwc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1594,7 +1594,7 @@ (define_insn "*mulhhwc"
(const_int 16))))]
"TARGET_MULHW"
"mulhhw. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mulhhw"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1606,7 +1606,7 @@ (define_insn "*mulhhw"
(const_int 16))))]
"TARGET_MULHW"
"mulhhw %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mulhhwuc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1626,7 +1626,7 @@ (define_insn "*mulhhwuc"
(const_int 16))))]
"TARGET_MULHW"
"mulhhwu. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mulhhwu"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1638,7 +1638,7 @@ (define_insn "*mulhhwu"
(const_int 16))))]
"TARGET_MULHW"
"mulhhwu %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mullhwc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1654,7 +1654,7 @@ (define_insn "*mullhwc"
(match_dup 2))))]
"TARGET_MULHW"
"mullhw. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mullhw"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1664,7 +1664,7 @@ (define_insn "*mullhw"
(match_operand:HI 2 "gpc_reg_operand" "r"))))]
"TARGET_MULHW"
"mullhw %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mullhwuc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1680,7 +1680,7 @@ (define_insn "*mullhwuc"
(match_dup 2))))]
"TARGET_MULHW"
"mullhwu. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mullhwu"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1690,7 +1690,7 @@ (define_insn "*mullhwu"
(match_operand:HI 2 "gpc_reg_operand" "r"))))]
"TARGET_MULHW"
"mullhwu %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
(define_insn "dlmzb"
diff --git a/gcc/config/rs6000/titan.md b/gcc/config/rs6000/titan.md
index 1adbee5..6bb4792 100644
--- a/gcc/config/rs6000/titan.md
+++ b/gcc/config/rs6000/titan.md
@@ -38,17 +38,13 @@ (define_insn_reservation "titan_fxu_adder" 1
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh")
-;; Keep the titan_imul and titan_mulhw (half-word) rules in order, to
-;; ensure the proper match: the half-word instructions are tagged as
-;; imul3 only, whereas regular multiplys will always carry a imul tag.
-
(define_insn_reservation "titan_imul" 5
- (and (eq_attr "type" "imul,imul2,imul_compare")
+ (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh,nothing*5,titan_fxu_wb")
(define_insn_reservation "titan_mulhw" 4
- (and (eq_attr "type" "imul3")
+ (and (eq_attr "type" "halfmul")
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh,nothing*4,titan_fxu_wb")
--
1.8.1.4
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