[GCC RFC]A new and simple pass merging paired load store instructions

[Jeff Law]

On 05/16/14 04:07, Bin.Cheng wrote:

> Yes, I think this one does have a good reason.  The target independent
> pass just makes sure that two consecutive memory access instructions
> are free of data-dependency with each other, then feeds it to back-end
> hook.  It's back-end's responsibility to generate correct instruction.
But given these two memory access insns, there's only a couple ways 
they're likely to combine into a single insn.  We could just as easily 
have the target independent code construct a new insn then try to 
recognize it.  If it's not recognized, then try the other way.

Or is it the case that we're doing something beyond upsizing the mode?


>   It's not about modifying an existing insn then recognize it, it's
> about creating new instruction sometimes.  For example, we can
> generate a simple move insn in Arm mode, while have to generate a
> parallel instruction in Thumb mode.  Target independent part has no
> idea how to generate an expected insn.  Moreover, back-end may check
> some special conditions too.
But can't you go through movXX to generate either the simple insn on the 
ARM or the PARALLEL on the thumb?

Jeff