[PATCH, ARM] Optimise NotDI AND/OR ZeroExtendSI for ARMv7A

[Ian Bolton]

> -----Original Message-----
> From: Richard Earnshaw
> Sent: 21 March 2014 13:57
> To: Ian Bolton
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH, ARM] Optimise NotDI AND/OR ZeroExtendSI for ARMv7A
> 
> On 19/03/14 16:53, Ian Bolton wrote:
> > This is a follow-on patch to one already committed:
> > http://gcc.gnu.org/ml/gcc-patches/2014-02/msg01128.html
> >
> > It implements patterns to simplify our RTL as follows:
> >
> > OR (Not:DI (A:DI), ZeroExtend:DI (B:SI))
> >   -->  the top half can be done with a MVN
> >
> > AND (Not:DI (A:DI), ZeroExtend:DI (B:SI))
> >   -->  the top half becomes zero.
> >
> > I've added test cases for both of these and also the existing
> > anddi_notdi patterns.  The tests all pass.
> >
> > Full regression runs passed.
> >
> > OK for stage 1?
> >
> > Cheers,
> > Ian
> >
> >
> > 2014-03-19  Ian Bolton  <ian.bolton@arm.com>
> >
> > gcc/
> > 	* config/arm/arm.md (*anddi_notdi_zesidi): New pattern
> > 	* config/arm/thumb2.md (*iordi_notdi_zesidi): New pattern.
> >
> > testsuite/
> > 	* gcc.target/arm/anddi_notdi-1.c: New test.
> > 	* gcc.target/arm/iordi_notdi-1.c: New test case.
> >
> >
> > arm-and-ior-notdi-zeroextend-patch-v1.txt
> >
> >
> > diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
> > index 2ddda02..d2d85ee 100644
> > --- a/gcc/config/arm/arm.md
> > +++ b/gcc/config/arm/arm.md
> > @@ -2962,6 +2962,28 @@
> >     (set_attr "type" "multiple")]
> >  )
> >
> > +(define_insn_and_split "*anddi_notdi_zesidi"
> > +  [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
> > +        (and:DI (not:DI (match_operand:DI 2 "s_register_operand"
> "0,?r"))
> > +                (zero_extend:DI
> > +                 (match_operand:SI 1 "s_register_operand" "r,r"))))]
> 
> The early clobber and register tying here is unnecessary.  All of the
> input operands are consumed in the first instruction, so you can
> eliminate the ties and the restriction on the overlap.  Something like
> (untested):
> 
> +(define_insn_and_split "*anddi_notdi_zesidi"
> +  [(set (match_operand:DI 0 "s_register_operand" "=r")
> +        (and:DI (not:DI (match_operand:DI 2 "s_register_operand" "r"))
> +                (zero_extend:DI
> +                 (match_operand:SI 1 "s_register_operand" "r"))))]
> 
> Ok for stage-1 with that change (though I'd recommend a another test
> run
> to validate the above).
> 
> R.

Thanks, Richard.  Regression runs came back OK with that change, so
I will consider this ready for stage 1.

The patch is attached for reference.
 
Cheers,
Ian


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