[PATCH AArch64] Fix aarch64_simd_valid_immediate for Bigendian

[James Greenhalgh]

On Mon, Mar 24, 2014 at 11:32:39AM +0000, Marcus Shawcroft wrote:
> On 21 March 2014 14:55, Alan Lawrence <alan.lawrence@arm.com> wrote:
> > This patch fixes a bug whereby a vector like V8QImode {1,0,1,0,1,0,1,0} can
> > result in an instruction like
> >
> > movi v1.4h, 0x1
> >
> > whereas on bigendian this should be
> >
> > movi v1.4h, 0x1, lsl 8
> >
> > Regression tested on aarch64_be-none-elf: no changes in libstdc++, newlib;
> > no regressions in gcc or g++ and FAIL->PASS as listed below.
> >
> > Ok for trunk (stage 4) ?
> 
> 
> > Cheers, Alan
> >
> > gcc/ChangeLog:
> >
> > 2014-03-21  Alan Lawrence  alan.lawrence@arm.com
> >
> >         * config/aarch64/aarch64.c (aarch64_simd_valid_immediate): reverse
> > order
> >         of elements for bigendian.
> 
> s/reverse/Reverse/
> 
> This should be fixed now in stage-4, the fix looks straight forward.
> If there are no objections from RM's in the next 24 hours go ahead and
> commit it.
> 

I've committed this on Alan's behalf as revision 208814, with the
ChangeLog below.

Thanks,
James

gcc/

2014-03-25  Alan Lawrence  <alan.lawrence@arm.com>

	* config/aarch64/aarch64.c (aarch64_simd_valid_immediate): Reverse
	order of elements for big-endian.