[PATCH, GCC/THUMB1] New define_insn_and_split pattern to enable optimizing out certain unnecessary uxtb instruction

[Terry Guo]

Hi

The existing test case gcc.target/arm/unsigned-extend-1.c fails for Thumb1
target like cortex-m0 because the thumb1_addsi3_addgeu insn pattern isn't
friendly to gcc combine pass. Before combine pass, we have such insn for
this test case:

(insn 10 9 12 2 (set (reg:SI 118)
        (plus:SI (plus:SI (reg:SI 120)
                (reg:SI 120))
            (geu:SI (reg:SI 119)
                (reg:SI 117))))

When the operand (reg:SI 120) is zero and operand (reg:SI 119) is constant
9, combine pass will turn this insn into:

(insn 10 9 12 2 (set (reg:SI 118)
                     (leu:SI (reg:SI 116) (const_int 9))))

Unfortunately this new insn doesn't match any existing patterns, this causes
combine pass to undo all attempts and results in sub-optimal code. The
attached patch intends to legitimize the new insn.

Tested with gcc regression test and no new regression.

Is it OK to trunk?

BR,
Terry

2014-03-17  Terry Guo  <terry.guo@arm.com>

        * config/arm/arm.md (cstoresi_leu_thumb1): New define_insn_and_split
pattern.
        (cstoresi4): Use above new pattern.

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