[Patch] Try to peephole2 QI *4 into SI on i386

[lin zuojian]

---
 gcc/config/i386/i386.md | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index b9f1320..86ab025 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -18535,6 +18535,55 @@
   [(set_attr "type" "other")
    (set_attr "length" "3")])
 
+(define_peephole2
+ [(set (mem:QI (match_operand 0 "register_operand"))
+					(match_operand 1 "const_int_operand"))
+	(set (mem:QI (plus (match_dup 0)
+							 (const_int 1)))
+			(match_operand 2 "const_int_operand"))
+	(set (mem:QI (plus (match_dup 0)
+							 (const_int 2)))
+			(match_operand 3 "const_int_operand"))
+	(set (mem:QI (plus (match_dup 0)
+							 (const_int 3)))
+			(match_operand 4 "const_int_operand"))]
+	""
+	[(set (mem:SI (match_dup 0))
+			(match_operand 5 "const_int_operand"))]
+{
+	int32_t _const = (INTVAL(operands[1]) & 0xff) | (((INTVAL(operands[2])) & 0xff)  << 8)
+												| (((INTVAL(operands[3])) & 0xff)  << 16) | (((INTVAL(operands[4])) & 0xff)  << 24);
+	operands[5] = gen_rtx_CONST_INT (SImode, _const);
+}
+)
+
+(define_peephole2
+ [(set (mem:QI (plus (match_operand 0 "register_operand")
+							 (match_operand 6 "const_int_operand")))
+					(match_operand 1 "const_int_operand"))
+	(set (mem:QI (plus (match_dup 0)
+							 (match_operand 7 "const_int_operand")))
+			(match_operand 2 "const_int_operand"))
+	(set (mem:QI (plus (match_dup 0)
+							 (match_operand 8 "const_int_operand")))
+			(match_operand 3 "const_int_operand"))
+	(set (mem:QI (plus (match_dup 0)
+							 (match_operand 9 "const_int_operand")))
+			(match_operand 4 "const_int_operand"))]
+	""
+	[(set (mem:SI (match_dup 0))
+			(match_operand 5 "const_int_operand"))]
+{
+	if ((INTVAL(operands[7]) - INTVAL(operands[6]) != 1)
+			&& (INTVAL(operands[8]) - INTVAL(operands[7]) != 1)
+			&& (INTVAL(operands[9]) - INTVAL(operands[8]) != 1))
+		FAIL;
+	int32_t _const = (INTVAL(operands[1]) & 0xff) | (((INTVAL(operands[2])) & 0xff)  << 8)
+												| (((INTVAL(operands[3])) & 0xff)  << 16) | (((INTVAL(operands[4])) & 0xff)  << 24);
+	operands[5] = gen_rtx_CONST_INT (SImode, _const);
+}
+)
+
 (include "mmx.md")
 (include "sse.md")
 (include "sync.md")
-- 
1.8.3.2


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