[AArch64] Make sure start callee-save offset for D registers aligned

[Jiong Wang]

For AArch64, there may have been an odd num core registers need to be saved.

This small patch ensure we remain 16 byte aligned for subsequent STP writes of D registers.

OK for trunk?

thanks.

gcc/
   * config/aarch64/aarch64.c (aarch64_layout_frame): Make sure start offset
     for vector registers in callee-saved area 16-byte aligned.

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