[AArch64/ARM 2/3] Recognize shuffle patterns for REV instructions on AArch64, rewrite intrinsics.

[Alan Lawrence]

I've pushed this as r211174, after merging with the EXT changes (r211058): the 
following instructions are equivalent

ext v<dest>.8b, v<src>.8b, v<src>.8b, #4
rev64 v<dest>.2s, v<src>.2s

and can both be output for a __builtin_shuffle mask of {1,0}. The latter seems 
more readable and so I've put the call to aarch64_evpc_rev ahead of the call to 
aarch64_evpc_ext in aarch64_expand_vec_perm_const_1. The actual patch I 
committed is attached.

Cheers, Alan

Marcus Shawcroft wrote:
> On 15 May 2014 16:52, Alan Lawrence <alan.lawrence@arm.com> wrote:
> 
>> 2014-05-15  Alan Lawrence  <alan.lawrence@arm.com>
>>
>>         * config/aarch64/aarch64-simd.md
>> (aarch64_rev<REVERSE:rev-op><mode>):
>>         New pattern.
>>         * config/aarch64/aarch64.c (aarch64_evpc_rev): New function.
>>         (aarch64_expand_vec_perm_const_1): Add call to aarch64_evpc_rev.
>>         * config/aarch64/iterators.md (REVERSE): New iterator.
>>         (UNSPEC_REV64, UNSPEC_REV32, UNSPEC_REV16): New enum elements.
>>         (rev_op): New int_attribute.
>>         * config/aarch64/arm_neon.h (vrev16_p8, vrev16_s8, vrev16_u8,
>>         vrev16q_p8, vrev16q_s8, vrev16q_u8, vrev32_p8, vrev32_p16,
>> vrev32_s8,
>>         vrev32_s16, vrev32_u8, vrev32_u16, vrev32q_p8, vrev32q_p16,
>> vrev32q_s8,
>>         vrev32q_s16, vrev32q_u8, vrev32q_u16, vrev64_f32, vrev64_p8,
>>         vrev64_p16, vrev64_s8, vrev64_s16, vrev64_s32, vrev64_u8,
>> vrev64_u16,
>>         vrev64_u32, vrev64q_f32, vrev64q_p8, vrev64q_p16, vrev64q_s8,
>>         vrev64q_s16, vrev64q_s32, vrev64q_u8, vrev64q_u16, vrev64q_u32):
>>         Replace temporary __asm__ with __builtin_shuffle.
> 
> OK /Marcus
> 
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