[PATCH] Vector mode addresses

Paulo Matos paulo@matos-sorge.com
Thu Jan 30 20:36:00 GMT 2014

On 30/01/14 14:01, Richard Biener wrote:
> I'm curious on where you are seeing MEMs with a vector mode address.
> What does that MEM even mean?

Yes, it looks strange but it was the way we came up with to implement an 
instruction that loads from a pair of addresses.

 From what I wrote previously to Richard.
"We have an instruction that loads two 32 bit values into a lower and 
upper parts of a 64bit register using a base register and a 64 bit 
register used as a double index.
r1 <- [r0, r2]
low(r1) = [r0 + low(r2)]
high(r1) = [r0 + high(r2)]"

>  From the referenced mail:
> new_rtx: (mem:V4SI (plus:V4SI (vec_concat:V4SI (vec_concat:V2SI
> (const_int 0 [0])
>                  (const_int 0 [0]))
>              (vec_concat:V2SI (const_int 0 [0])
>                  (const_int 0 [0])))
> that should be invalid and somehow lacks the subreg:DI.  The bug is where
> that got lost.

I don't think it got lost. GCC was trying to simplify it. That's why my 
patch was in simplify_subreg. GCC was trying to simplify a subreg in 
DImode with this mem rtx as SUBREG_REG and offset 8.

Paulo Matos

More information about the Gcc-patches mailing list