[committed] TILE-Gx: fix atomic_fetch_sub pattern.

Walter Lee walt@tilera.com
Sat Jan 25 20:50:00 GMT 2014


This patch fixes a bug in the atomic_fetch_sub pattern.	 The negation
is wrong and a register was getting clobbered.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5d7adb7..15e9194 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,10 @@
 2014-01-25  Walter Lee  <walt@tilera.com>
 
+	* config/tilegx/sync.md (atomic_fetch_sub): Fix negation and
+	avoid clobbering a live register.
+
+2014-01-25  Walter Lee  <walt@tilera.com>
+
 	* config/tilegx/tilegx-c.c (tilegx_cpu_cpp_builtins): 
 	Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2}.
 	* config/tilegx/tilepro-c.c (tilepro_cpu_cpp_builtins): 
diff --git a/gcc/config/tilegx/sync.md b/gcc/config/tilegx/sync.md
index 5860257..3d93493 100644
--- a/gcc/config/tilegx/sync.md
+++ b/gcc/config/tilegx/sync.md
@@ -150,15 +150,22 @@
    (match_operand:SI 3 "const_int_operand" "")]         ;; model
   ""
 {
+  rtx addend;
   enum memmodel model = (enum memmodel) INTVAL (operands[3]);
 
   if (operands[2] != const0_rtx)
-    emit_move_insn (operands[2], gen_rtx_NEG (<MODE>mode, operands[2]));
+    {
+       addend = gen_reg_rtx (<MODE>mode);
+       emit_move_insn (addend,
+                       gen_rtx_MINUS (<MODE>mode, const0_rtx, operands[2]));
+    }
+  else
+    addend = operands[2];
 
   tilegx_pre_atomic_barrier (model);
   emit_insn (gen_atomic_fetch_add_bare<mode> (operands[0],
                                               operands[1],
-                                              operands[2]));
+                                              addend));
   tilegx_post_atomic_barrier (model);
   DONE;
 })



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