[Patch,AArch64] Support SISD variants of SCVTF,UCVTF

Marcus Shawcroft marcus.shawcroft@gmail.com
Tue Jan 21 13:35:00 GMT 2014

On 13 January 2014 19:27, Vidya Praveen <vidyapraveen@arm.com> wrote:
> Hello,
> This patch adds support to the SISD variants of SCVTF/UCVTF instructions.
> This also refactors the existing support for floating point instruction
> variants of SCVTF/UCVTF in order to direct the instruction selection based
> on the constraints. Given that the floating-point variations supports
> inequal width convertions (SI to DF and DI to SF), new mode iterator w1 and
> w2 have been introduced and fcvt_target,FCVT_TARGET have been extended to
> support non vector type. Since this patch changes the existing patterns, the
> testcase includes tests for both SISD and floating point variations of the
> instructions.
> Tested for aarch64-none-elf.
> OK for trunk?

OK but wait for stage-1.

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