[Patch,AArch64] Support SISD variants of SCVTF,UCVTF

Vidya Praveen vidyapraveen@arm.com
Mon Jan 13 19:27:00 GMT 2014


Hello,

This patch adds support to the SISD variants of SCVTF/UCVTF instructions.
This also refactors the existing support for floating point instruction
variants of SCVTF/UCVTF in order to direct the instruction selection based
on the constraints. Given that the floating-point variations supports
inequal width convertions (SI to DF and DI to SF), new mode iterator w1 and
w2 have been introduced and fcvt_target,FCVT_TARGET have been extended to
support non vector type. Since this patch changes the existing patterns, the
testcase includes tests for both SISD and floating point variations of the
instructions.

Tested for aarch64-none-elf.

OK for trunk?

Cheers
VP.

gcc/ChangeLog:

2013-01-13  Vidya Praveen  <vidyapraveen@arm.com>

	* aarch64.md (float<GPI:mode><GPF:mode>2): Remove.
	(floatuns<GPI:mode><GPF:mode>2): Remove.
	(<optab><fcvt_target><GPF:mode>2): New pattern for equal width float
	and floatuns conversions.
	(<optab><fcvt_iesize><GPF:mode>2): New pattern for inequal width float
	and floatuns conversions.
	* iterators.md (fcvt_target, FCVT_TARGET): Support SF and DF modes.
	(w1,w2): New mode attributes for inequal width conversions.

gcc/testsuite/ChangeLog:

2013-01-13  Vidya Praveen  <vidyapraveen@arm.com>

	* gcc.target/aarch64/cvtf_1.c: New.
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