[PATCH][AArch64] vrnd<*>_f64 patch for stage-1

[Alex Velenko]

On 13/02/14 17:43, Richard Henderson wrote:
> On 02/13/2014 03:17 AM, Alex Velenko wrote:
>> +/* Sets "rmode" field of "FPCR" control register to
>> +   "FPROUNDING_ZERO".  */
>
> Comment is wrong, or at least misleading.
>
>> +void __inline __attribute__ ((__always_inline__))
>> +set_rounding_mode (uint32_t mode)
>> +{
>> +  uint32_t r;
>> +
>> +  /* Read current FPCR.  */
>> +  asm volatile ("mrs %[r], fpcr" : [r] "=r" (r) : :);
>> +
>> +  /* Clear rmode.  */
>> +  r &= 3 << RMODE_START;
>
>    ~(3 << RMODE_START)
>
>> +  /* Calculate desired FPCR.  */
>> +  r |= mode << RMODE_START;
>> +
>> +  /* Write desired FPCR back.  */
>> +  asm volatile ("msr fpcr, %[r]" : : [r] "r" (r) :);
>> +}
>
> Fortunately for this testcase, you do always use FPROUNDING_ZERO == 3 when
> calling this function, so the bugs are hidden.
>
>
> r~
>

Hi Richard,
Thank you for pointing those issue out. here is a respin of the same 
patch with indecated issues fixed. the description of the patch is as 
follows:

This patch adds vrnd<*>_f64 aarch64 intrinsics. A testcase for those
intrinsics is added. Run a complete LE and BE regression run with no 
regressions.

Is patch OK for stage-1?

gcc/

2014-02-21  Alex Velenko  <Alex.Velenko@arm.com>

     * config/aarch64/aarch64-builtins.c (BUILTIN_VDQF_DF): Macro
     added.
     * config/aarch64/aarch64-simd-builtins.def (frintn): Use added
     macro.
     * config/aarch64/aarch64-simd.md (<frint_pattern>): Comment
     corrected.
     * config/aarch64/aarch64.md (<frint_pattern>): Likewise.
     * config/aarch64/arm_neon.h (vrnd_f64): Added.
     (vrnda_f64): Likewise.
     (vrndi_f64): Likewise.
     (vrndm_f64): Likewise.
     (vrndn_f64): Likewise.
     (vrndp_f64): Likewise.
     (vrndx_f64): Likewise.

gcc/testsuite/

2014-02-21  Alex Velenko  <Alex.Velenko@arm.com>

     gcc.target/aarch64/vrnd_f64_1.c : New testcase.


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