[PATCH] PR middle-end/60281

[lin zuojian]

ÓÚ 2014Äê02ÔÂ20ÈÕ 19:05, Ramana Radhakrishnan дµÀ:
>>> Or, if ARM supports unaligned loads/stores using special instructions,
>>> perhaps you should also benchmark the alternative of not realigning, but
>>> instead making sure those unaligned instructions are used for the shadow
>>> memory loads/stores in the asan prologue/epilogue.
>> I have tried to use -fno-peephole2 to shutdown instructions
>> combinations,but that makes me feel uncomfortable.
> That should not be required. I suspect what you need is a
> movmisalignsi expander generating unaligned_store/loadsi patterns.
> Notice that these put out ldr / str instructions but with UNSPECs
> which means that the peepholers for ldrd / ldm will not catch them.
>
> As Jakub says later in this thread ARM is a STRICT_ALIGNMENT target.
> If the compiler is peepholing unaligned ldr's and str's, that would be
> a bug and the compiler needs to be fixed to avoid this.
>
> regards
> Ramana
That is not a bug of instruction selection.SImode implies that the
address is 4 bytes aligned.
>
>>> Please next time post the patch from a sane MUA that doesn't eat tabs or
>>> at least as an attachment.  Comments should start with a capital letter, and
>>> with a full stop followed by two spaces, in the ChangeLog also all entries
>>> should end with a full stop.
>> Sorry about that...
>> BTW,I didn't modify the ChangeLog because this patch should be discussed
>> carefully.
>>>       Jakub
>>