[PATCH, ARM][PING] Reintroduce minipool ranges for zero-extension insn patterns
Ramana Radhakrishnan
ramana.gcc@googlemail.com
Mon Feb 3 15:22:00 GMT 2014
On Mon, Feb 3, 2014 at 3:14 PM, Yury Gribov <y.gribov@samsung.com> wrote:
>> Additionally I'm not really sure
>> why there is an additional load from the constant pool here - what is
>> the constant in this case ?
>> Given it is atmost a 16 bit constant
>> surely that should be loaded with a single mov(w) instruction
>> in armv7 land.
>
> I've made some investigations with 4.8.
>
> The problematic RTL is
>
> (insn 1191 1190 1192 142 (set (reg:SI 1 r1)
> (zero_extend:SI (subreg:HI (reg:SI 2606) 0))) svga_tgsi_emit.h:165 165
> {*arm_zero_extendhisi2_v6}
> (nil))
>
> where RHS expression gets replaced with equivalent constant:
>
> (const_int 1 [0x1])
Uggh - what a mess. Surely that zero_extend:SI (const_int 1) should be
replaced by a move somewhere.
Ramana
More information about the Gcc-patches
mailing list