Fix vec_extract_lo constraint.

[Uros Bizjak]

On Tue, Aug 5, 2014 at 2:43 PM, Ilya Tocar <tocarip.intel@gmail.com> wrote:
> Hi,
> I've noticed that vec_extract_lo_<mode><mask_name> pattern has
> vm/vm alternative when mask is not applied. This can lead to insn
> with 2 memory operands. Patch bellow fixes it.
> Ok for trunk?
>
> 2014-08-05  Ilya Tocar  <ilya.tocar@intel.com>
>
>         * common/config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Fix
>         constraint.
>
> ---
>  gcc/config/i386/sse.md | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 0f7ca27..85f48ab 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -5999,9 +5999,9 @@
>     (set_attr "mode" "<sseinsnmode>")])
>
>  (define_insn "vec_extract_lo_<mode><mask_name>"
> -  [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=<store_mask_constraint>")
> +  [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=v,<store_mask_constraint>")
>         (vec_select:<ssehalfvecmode>
> -         (match_operand:V8FI 1 "nonimmediate_operand" "vm")
> +         (match_operand:V8FI 1 "nonimmediate_operand" "vm,v")
>           (parallel [(const_int 0) (const_int 1)
>              (const_int 2) (const_int 3)])))]
>    "TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1]))"

I'd suggest op0: "=<store_mask_constraint>,v" and op1: "v,m". This
would result in op0:"=vm,v" op1:"v,m" and op0:"=v,v" op1:"v,m".

Uros.