[Patch AArch64] Fix register constraints for lane intrinsics.

[James Greenhalgh]

Hi,

Most of the vector-by-element instructions in AArch64 have the restriction
that, if the vector they are taking an element from has type "h"
then it must be in a register from the lower half of the vector register
set (i.e. v0-v15). While we have imposed that restriction in places, we
have not been consistent.

Fix that.

Tested with aarch64.exp with no regressions.

OK for trunk?

Thanks,
James

---
gcc/

2013-09-06  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-simd.md
	(aarch64_sqdml<SBINQOPS:as>l_n<mode>_internal): Use
	<vwx> iterator to ensure correct register choice.
	(aarch64_sqdml<SBINQOPS:as>l2_n<mode>_internal): Likewise.
	(aarch64_sqdmull_n<mode>): Likewise.
	(aarch64_sqdmull2_n<mode>_internal): Likewise.
	* config/aarch64/arm_neon.h
	(vml<as><q>_lane<q>_<su>16): Use 'x' constraint for element vector.
	(vml<as><q>_n_<su>16): Likewise.
	(vml<as>l_high_lane<q>_<su>16): Likewise.
	(vml<as>l_high_n_<su>16): Likewise.
	(vml<as>l_lane<q>_<su>16): Likewise.
	(vml<as>l_n_<su>16): Likewise.
	(vmul<q>_lane<q>_<su>16): Likewise.
	(vmul<q>_n_<su>16): Likewise.
	(vmull_lane<q>_<su>16): Likewise.
	(vmull_n_<su>16): Likewise.
	(vmull_high_lane<q>_<su>16): Likewise.
	(vmull_high_n_<su>16): Likewise.
	(vqrdmulh<q>_n_s16): Likewise.
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