[PATCH] PowerPC merge TD/TF moves

Michael Meissner meissner@linux.vnet.ibm.com
Mon Mar 11 19:05:00 GMT 2013


On Thu, Mar 07, 2013 at 08:45:10PM -0500, David Edelsohn wrote:
> On Wed, Jan 30, 2013 at 5:50 PM, Michael Meissner
> <meissner@linux.vnet.ibm.com> wrote:
> > This patch like the previous 2 pages combines the decimal and binary floating
> > point moves, this time for 128-bit floating point.
> >
> > In doing this patch, I discovered that I left out the code in the previous
> > patch to enable the wg constraint to enable -mcpu=power6x to utilize the direct
> > move instructions.  So, I added the code in this patch, and also created a test
> > to make sure that direct moves are generated in the future.
> >
> > I also added the reload helper for DDmode to rs6000_vector_reload that was
> > missed in the last patch.  This was harmless, since that is only used with an
> > undocumented debug switch.  Hopefully sometime in the future, I will scalar
> > floating point to be able to be loaded in the upper 32 VSX registers that are
> > overlaid over the Altivec registers.
> >
> > Like the previous 2 patches, I've bootstrapped this, and ran make check with no
> > regressions.  Is it ok to apply when GCC 4.9 opens up?
> >
> > I have one more patch in the insn combination to post, combining movdi on
> > systems with normal floating point and with the power6 direct move
> > instructions.
> 
> Mike,
> 
> Which of these sets of patches adjusts and updates
> rs6000_register_move_cost for -mfpgpr and for VSRs and FPRs sharing
> the same register file?

None of these patches adjust register_move_cost.

-- 
Michael Meissner, IBM
Now:      M/S 2757, 5 Technology Place Drive, Westford, MA 01886-3141, USA
March 20: M/S 2506R, 550 King Street, Littleton, MA 01460, USA
meissner@linux.vnet.ibm.com	fax +1 (978) 399-6899



More information about the Gcc-patches mailing list