[PATCH, AArch64] Make zero_extends explicit for some SImode patterns

Ian Bolton ian.bolton@arm.com
Tue Jan 15 16:14:00 GMT 2013

I've made zero_extend versions of SI mode patterns that write
to W registers in order to make the implicit zero_extend that
they do explicit, so GCC can be smarter about when it actually
needs to plant a zero_extend (uxtw).

If that sounds familiar, it's because this patch continues the
work of one already committed. :)

This has been regression-tested for linux and bare-metal.

OK for trunk and backport to ARM/aarch64-4.7-branch?


2013-01-15  Ian Bolton  <ian.bolton@arm.com>

	* gcc/config/aarch64/aarch64.md
	(*cstoresi_neg_uxtw): New pattern.
	(*cmovsi_insn_uxtw): New pattern.
	(*<optab>si3_uxtw): New pattern.
	(*<LOGICAL:optab>_<SHIFT:optab>si3_uxtw): New pattern.
	(*<optab>si3_insn_uxtw): New pattern.
	(*bswapsi2_uxtw): New pattern.
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