[AArch64] __atomic_thread_fence and release memory model

Yvan Roux yvan.roux@linaro.org
Thu Feb 14 15:41:00 GMT 2013


a call to the builtin __atomic_thread_fence with the memory model
__ATOMIC_RELEASE generates a data memory barrier with the option ish
whereas I think that the one which has the "release" semantic is ishst
(store before store). The attached patch implements my proposal.



2013-02-14  Yvan Roux  <yvan.roux@linaro.org>

        * config/aarch64/atomics.md (dmb): Emit release mode barrier.
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