[AArch64] __atomic_thread_fence and release memory model

Yvan Roux yvan.roux@linaro.org
Thu Feb 14 15:41:00 GMT 2013


Hi,

a call to the builtin __atomic_thread_fence with the memory model
__ATOMIC_RELEASE generates a data memory barrier with the option ish
whereas I think that the one which has the "release" semantic is ishst
(store before store). The attached patch implements my proposal.

Thanks,
Yvan

--
gcc/

2013-02-14  Yvan Roux  <yvan.roux@linaro.org>

        * config/aarch64/atomics.md (dmb): Emit release mode barrier.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 0001-AArch64-fix-data-memory-barrier-release-mode.patch
Type: application/octet-stream
Size: 440 bytes
Desc: not available
URL: <http://gcc.gnu.org/pipermail/gcc-patches/attachments/20130214/64485bcc/attachment.obj>


More information about the Gcc-patches mailing list