[AArch64] Add special case when expanding vcond with arms {-1, -1}, {0, 0}.

[Marcus Shawcroft]

OK
/Marcus

On 30 April 2013 16:06, James Greenhalgh <james.greenhalgh@arm.com> wrote:
>
> If the end goal of a VEC_COND_EXPR is to pick between
> {-1, -1, -1, -1} and {0, 0, 0, 0}
> then we do not need to do a bit select, this is just
> a move of the generated mask to the result operand.
>
> This patch checks for this case, and emits the
> appropriate instructions. This can save us loading the
> two constant masks and performing a bsl.
>
> The midend turns GE_EXPR style tree codes in to VEC_COND_EXPRS,
> so fixing this folding up earlier in the compiler is not helpful.
>
> Regression tested for aarch64-none-elf with no regressions.
>
> OK?
>
> Thanks,
> James
>
> ---
> gcc/
>
> 2013-04-30  James Greenhalgh  <james.greenhalgh@arm.com>
>
>         * config/aarch64/aarch64-simd.md
>         (vcond<mode>_internal): Handle special cases for constant masks.
>         (vcond<mode><mode>): Allow nonmemory_operands for outcome vectors.
>         (vcondu<mode><mode>): Likewise.
>         (vcond<v_cmp_result><mode>): New.