RFA: patch to fix PR19398

[Vladimir Makarov]

The following patch fixes

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19398

Uros, there is i386.md part for which I need an approval.  Without this 
change, GCC will still generate the same code even if LRA uses an 
alternative with 'm' constraint.

2012-11-18  Vladimir Makarov  <vmakarov@redhat.com>

         PR target/19398
         * lra-constraints.c (process_alt_operands): Discourage reloads
         through secodnary memory.
         * config/i386/i386.md (fix_trunc?f?i_sse): Remove peephole2
         patterns.

-------------- next part --------------
Index: lra-constraints.c
===================================================================
--- lra-constraints.c	(revision 193567)
+++ lra-constraints.c	(working copy)
@@ -1942,6 +1942,19 @@
 	      if (no_regs_p && REG_P (op))
 		reject++;
 
+#ifdef SECONDARY_MEMORY_NEEDED
+	      /* If reload requires moving value through secondary
+		 memory, it will need one more insn at least.  */
+	      if (this_alternative != NO_REGS 
+		  && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS
+		  && ((curr_static_id->operand[nop].type != OP_OUT
+		       && SECONDARY_MEMORY_NEEDED (cl, this_alternative,
+						   GET_MODE (op)))
+		      || (curr_static_id->operand[nop].type != OP_IN
+			  && SECONDARY_MEMORY_NEEDED (this_alternative, cl,
+						      GET_MODE (op)))))
+		losers++;
+#endif
 	      /* Input reloads can be inherited more often than output
 		 reloads can be removed, so penalize output
 		 reloads.  */
Index: config/i386/i386.md
===================================================================
--- config/i386/i386.md	(revision 193557)
+++ config/i386/i386.md	(working copy)
@@ -1875,7 +1875,7 @@
 	      (const_string "OI")))])
 
 (define_insn "*movti_internal_rex64"
-  [(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,o  ,x,x ,m")
+  [(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,!o  ,x,x ,m")
 	(match_operand:TI 1 "general_operand"      "riFo,riF,C,xm,x"))]
   "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
 {
@@ -4503,23 +4503,6 @@
    && peep2_reg_dead_p (2, operands[0])"
   [(set (match_dup 2) (fix:SWI48x (match_dup 1)))])
 
-;; Avoid vector decoded forms of the instruction.
-(define_peephole2
-  [(match_scratch:DF 2 "x")
-   (set (match_operand:SWI48x 0 "register_operand")
-	(fix:SWI48x (match_operand:DF 1 "memory_operand")))]
-  "TARGET_SSE2 && TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_dup 0) (fix:SWI48x (match_dup 2)))])
-
-(define_peephole2
-  [(match_scratch:SF 2 "x")
-   (set (match_operand:SWI48x 0 "register_operand")
-	(fix:SWI48x (match_operand:SF 1 "memory_operand")))]
-  "TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_dup 0) (fix:SWI48x (match_dup 2)))])
-
 (define_insn_and_split "fix_trunc<mode>_fisttp_i387_1"
   [(set (match_operand:SWI248x 0 "nonimmediate_operand")
 	(fix:SWI248x (match_operand 1 "register_operand")))]