[PATCH 3/7] s390: Use risbgz for AND.
Andreas Krebbel
krebbel@linux.vnet.ibm.com
Tue Nov 6 14:29:00 GMT 2012
I didn't do any changes to that one. So it is only a refresh to latest
GCC head.
Bootstrapped on s390x with -march=z196. No regressions.
Feel free to apply.
Thanks!
Bye,
-Andreas-
gcc/config/s390/s390.md | 109 +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1 file changed, 4 insertions(+), 105 modifications(!)
Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig
--- gcc/config/s390/s390.md
***************
*** 6000,6043 ****
(define_insn "*anddi3_cc"
[(set (reg CC_REGNUM)
! (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
! (match_operand:DI 2 "general_operand" " d,d,RT"))
! (const_int 0)))
! (set (match_operand:DI 0 "register_operand" "=d,d, d")
(and:DI (match_dup 1) (match_dup 2)))]
! "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
ngr\t%0,%2
ngrk\t%0,%1,%2
! ng\t%0,%2"
! [(set_attr "op_type" "RRE,RRF,RXY")
! (set_attr "cpu_facility" "*,z196,*")
! (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
(define_insn "*anddi3_cconly"
[(set (reg CC_REGNUM)
! (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
! (match_operand:DI 2 "general_operand" " d,d,RT"))
! (const_int 0)))
! (clobber (match_scratch:DI 0 "=d,d, d"))]
! "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH
/* Do not steal TM patterns. */
&& s390_single_part (operands[2], DImode, HImode, 0) < 0"
"@
ngr\t%0,%2
ngrk\t%0,%1,%2
! ng\t%0,%2"
! [(set_attr "op_type" "RRE,RRF,RXY")
! (set_attr "cpu_facility" "*,z196,*")
! (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
(define_insn "*anddi3"
[(set (match_operand:DI 0 "nonimmediate_operand"
! "=d,d, d, d, d, d, d, d,d,d, d, AQ,Q")
! (and:DI (match_operand:DI 1 "nonimmediate_operand"
! "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
! (match_operand:DI 2 "general_operand"
! "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxQDF,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
--- 6000,6049 ----
(define_insn "*anddi3_cc"
[(set (reg CC_REGNUM)
! (compare
! (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
! (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
! (const_int 0)))
! (set (match_operand:DI 0 "register_operand" "=d,d, d, d")
(and:DI (match_dup 1) (match_dup 2)))]
! "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
"@
ngr\t%0,%2
ngrk\t%0,%1,%2
! ng\t%0,%2
! risbg\t%0,%1,%s2,128+%e2,0"
! [(set_attr "op_type" "RRE,RRF,RXY,RIE")
! (set_attr "cpu_facility" "*,z196,*,z10")
! (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
(define_insn "*anddi3_cconly"
[(set (reg CC_REGNUM)
! (compare
! (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
! (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
! (const_int 0)))
! (clobber (match_scratch:DI 0 "=d,d, d, d"))]
! "TARGET_ZARCH
! && s390_match_ccmode(insn, CCTmode)
/* Do not steal TM patterns. */
&& s390_single_part (operands[2], DImode, HImode, 0) < 0"
"@
ngr\t%0,%2
ngrk\t%0,%1,%2
! ng\t%0,%2
! risbg\t%0,%1,%s2,128+%e2,0"
! [(set_attr "op_type" "RRE,RRF,RXY,RIE")
! (set_attr "cpu_facility" "*,z196,*,z10")
! (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
(define_insn "*anddi3"
[(set (match_operand:DI 0 "nonimmediate_operand"
! "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q")
! (and:DI
! (match_operand:DI 1 "nonimmediate_operand"
! "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0")
! (match_operand:DI 2 "general_operand"
! "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
***************
*** 6052,6061 ****
ngr\t%0,%2
ngrk\t%0,%1,%2
ng\t%0,%2
#
#"
! [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
! (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,*,*")
(set_attr "z10prop" "*,
*,
z10_super_E1,
--- 6058,6068 ----
ngr\t%0,%2
ngrk\t%0,%1,%2
ng\t%0,%2
+ risbg\t%0,%1,%s2,128+%e2,0
#
#"
! [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
! (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
(set_attr "z10prop" "*,
*,
z10_super_E1,
***************
*** 6067,6072 ****
--- 6074,6080 ----
z10_super_E1,
*,
z10_super_E1,
+ z10_super_E1,
*,
*")])
***************
*** 6087,6096 ****
(define_insn "*andsi3_cc"
[(set (reg CC_REGNUM)
! (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
! (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
! (const_int 0)))
! (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
(and:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
--- 6095,6106 ----
(define_insn "*andsi3_cc"
[(set (reg CC_REGNUM)
! (compare
! (and:SI
! (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
! (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
! (const_int 0)))
! (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
(and:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
***************
*** 6098,6114 ****
nr\t%0,%2
nrk\t%0,%1,%2
n\t%0,%2
! ny\t%0,%2"
! [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
! (set_attr "cpu_facility" "*,*,z196,*,*")
! (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
(define_insn "*andsi3_cconly"
[(set (reg CC_REGNUM)
! (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
! (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
! (const_int 0)))
! (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
"s390_match_ccmode(insn, CCTmode)
/* Do not steal TM patterns. */
&& s390_single_part (operands[2], SImode, HImode, 0) < 0"
--- 6108,6128 ----
nr\t%0,%2
nrk\t%0,%1,%2
n\t%0,%2
! ny\t%0,%2
! risbg\t%0,%1,%t2,128+%f2,0"
! [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
! (set_attr "cpu_facility" "*,*,z196,*,*,z10")
! (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
! z10_super_E1,z10_super_E1,z10_super_E1")])
(define_insn "*andsi3_cconly"
[(set (reg CC_REGNUM)
! (compare
! (and:SI
! (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
! (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
! (const_int 0)))
! (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
"s390_match_ccmode(insn, CCTmode)
/* Do not steal TM patterns. */
&& s390_single_part (operands[2], SImode, HImode, 0) < 0"
***************
*** 6117,6135 ****
nr\t%0,%2
nrk\t%0,%1,%2
n\t%0,%2
! ny\t%0,%2"
! [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
! (set_attr "cpu_facility" "*,*,z196,*,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
! z10_super_E1,z10_super_E1")])
(define_insn "*andsi3_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand"
! "=d,d, d, d, d,d,d,d,d, AQ,Q")
(and:SI (match_operand:SI 1 "nonimmediate_operand"
! "%d,o, 0, 0, 0,0,d,0,0, 0,0")
(match_operand:SI 2 "general_operand"
! " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxQSF,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
--- 6131,6150 ----
nr\t%0,%2
nrk\t%0,%1,%2
n\t%0,%2
! ny\t%0,%2
! risbg\t%0,%1,%t2,128+%f2,0"
! [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
! (set_attr "cpu_facility" "*,*,z196,*,*,z10")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
! z10_super_E1,z10_super_E1,z10_super_E1")])
(define_insn "*andsi3_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand"
! "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
(and:SI (match_operand:SI 1 "nonimmediate_operand"
! "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
(match_operand:SI 2 "general_operand"
! " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
***************
*** 6142,6151 ****
nrk\t%0,%1,%2
n\t%0,%2
ny\t%0,%2
#
#"
! [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
! (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,*,*")
(set_attr "z10prop" "*,
*,
z10_super_E1,
--- 6157,6167 ----
nrk\t%0,%1,%2
n\t%0,%2
ny\t%0,%2
+ risbg\t%0,%1,%t2,128+%f2,0
#
#"
! [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
! (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
(set_attr "z10prop" "*,
*,
z10_super_E1,
***************
*** 6155,6160 ****
--- 6171,6177 ----
*,
z10_super_E1,
z10_super_E1,
+ z10_super_E1,
*,
*")])
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