[PATCH,ARM] Improve peepholes for LDM with commutative operators

[Greta Yorsh]

This patch improves existing peephole optimizations that merge individual
LDRs into LDM, in the case that the order of registers in LDR instructions
is not ascending, but the loaded values can be reordered because their uses
commute. 

There are two changes:
* use rtx__equal_p to compare operands (instead of plain ==)
* identify more cases of dead registers in the pattern.

For example, the following sequence
    LDR r1, [r2]
    LDR r0, [r2, #4]
    ADD r0, r0, r1
can be transformed into
    LDRD r0, r1, [r2]
    ADD r0, r0, r1
when r1 is dead after ADD. Such optimization opportunities are missed by the
existing peephole conditions, because r0 is not dead after ADD. This patch
enables such transformations.

No regression on qemu for --target=arm-none-eabi --with-cpu=cortex-a15 and
a9.

This patch was originally submitted as part of a sequence of patches
improving LDRD/STRD/LDM/STM generation:
http://gcc.gnu.org/ml/gcc-patches/2011-11/msg00920.html
but it is independent and it fixes a failures in one of the regression
tests:
PASS: gcc.target/arm/pr40457-1.c scan-assembler ldm

Is it OK for GCC 4.7 Stage 4 ?

Thank you,

Greta

gcc/ChangeLog

2012-02-28  Greta Yorsh  <Greta.Yorsh@arm.com>

        * config/arm/arm-ldmstm.ml: Improved conditions of peepholes that
generate
        LDM followed by a commutative operator.
        * config/arm/ldmstm.md: Regenerated.
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