PATCH: PR target/52146: [x32] - Wrong code to access addresses 0x80000000 to 0xFFFFFFFF

H.J. Lu hongjiu.lu@intel.com
Fri Feb 10 17:44:00 GMT 2012


On Fri, Feb 10, 2012 at 09:25:06AM -0800, H.J. Lu wrote:
> Hi,
> 
> Since constant address in x32 is signed extended to 64bit, negative
> displacement without base nor index is out of range.  OK for trunk?
> 

Here is a different patch.

H.J.
---
gcc/

2012-02-10  Uros Bizjak  <ubizjak@gmail.com>

	PR target/52146
	* config/i386/i386.c (ix86_legitimate_address_p): Disallow
	negative constant address for x32.

gcc/testsuite/

2012-02-10  H.J. Lu  <hongjiu.lu@intel.com>

	PR target/52146
	* gcc.target/i386/pr52146.c: New.

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 009dd53..8f4e72e 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -11932,6 +11932,13 @@ ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
   rtx base, index, disp;
   HOST_WIDE_INT scale;
 
+  /* Since constant address in x32 is signed extended to 64bit,
+     we have to prevent addresses from 0x80000000 to 0xffffffff.  */
+  if (TARGET_X32
+      && CONST_INT_P (addr)
+      && val_signbit_known_set_p (SImode, INTVAL (addr)))
+    return false;
+
   if (ix86_decompose_address (addr, &parts) <= 0)
     /* Decomposition failed.  */
     return false;
diff --git a/gcc/testsuite/gcc.target/i386/pr52146.c b/gcc/testsuite/gcc.target/i386/pr52146.c
new file mode 100644
index 0000000..68bdeff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr52146.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target { { i?86-*-linux* x86_64-*-linux* } && { ! { ia32 } } } } } */
+/* { dg-options "-O2 -mx32" } */
+
+void test1() {
+  int* apic_tpr_addr = (int *)0xfee00080;
+  *apic_tpr_addr += 4;
+}
+void test2() {
+  volatile int* apic_tpr_addr = (int *)0xfee00080;
+  *apic_tpr_addr = 0;
+}
+void test3() {
+  volatile int* apic_tpr_addr = (int *)0x7fffffff;
+  *apic_tpr_addr = 0;
+}
+
+/* { dg-final { scan-assembler-not "-18874240" } } */



More information about the Gcc-patches mailing list