[SH] PR 51244 - Improve store of floating-point comparison

[Oleg Endo]

Hello,

This patch mainly improves stores of negated/inverted floating point
comparison results in regs and removes a useless zero-extension after
storing the negated T bit in a reg.

One thing that is annoying is the fact that the '-1' constant is emitted
during combine and thus won't get any chance of being CSE-ed in any way.
This results in multiple regs being loaded with the '-1' constant,
although one would suffice.
For integer comparisons, I've fixed this a while ago by loading the
constant '-1' into a reg in the expander and emitting an insn that
'uses' that reg.  However, this won't work for floating-point
comparisons, because the cstoresf expander never sees the inversion.

Is there a way to somehow merge pseudos that will be loaded with the
same constant values before register allocation, possibly also lifting
those constant loads outside of loops?

Tested on rev 190151 with
 make -k check RUNTESTFLAGS="--target_board=sh-sim
\{-m2/-ml,-m2/-mb,-m2a/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}"

and no new failures.
OK?

Cheers,
Oleg

ChangeLog:
	PR target/51244
	* config/sh/sh.md: Add negc extu sequence peephole.
	(movrt, movnegt, movrt_negc, nott): Use t_reg_operand predicate.
	(*movrt_negc): New insn.
	* config/sh/sync.md (atomic_test_and_set): Pass gen_t_reg_rtx to
	gen_movnegt.
	* config/sh/sh.c (expand_cbranchsi4, sh_emit_scc_to_t, 
	sh_emit_compare_and_branch, sh_emit_compare_and_set): Use
	get_t_reg_rtx.
	(sh_expand_t_scc): Pass gen_t_reg_rtx to gen_movnegt.

testsuite/ChangeLog:
	PR target/51244
	* gcc.target/sh/pr51244-5: New.
	* gcc.target/sh/pr51244-6: New.
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