[PATCH] Improve Niagara-3 tuning.
David Miller
davem@davemloft.net
Sun Sep 18 09:00:00 GMT 2011
This adjusts the costs of various operations on Niagara-3, in
particular FP operation latency increases to 9 cycles compared to
Niagara-2's 6 cycles. Integer multiplies increase to 9 cycles as
well, which likely indicates that they go through the FPU unit too.
I also fixed up the integer divide costs for Niagara-2, as it's
pretty clear I have no clue how to compute averages :-)
Commited to trunk.
gcc/
* gcc/config/sparc/sparc.c (niagara2_costs): Adjust integer
divide costs.
(niagara3_costs): New.
(sparc_option_override): Use it.
* gcc/config/sparc/niagara2.md: Adjust with more accurate
Niagara-3 reservations.
diff --git a/gcc/config/sparc/niagara2.md b/gcc/config/sparc/niagara2.md
index 999e13b..d53be84 100644
--- a/gcc/config/sparc/niagara2.md
+++ b/gcc/config/sparc/niagara2.md
@@ -45,12 +45,22 @@
"niag2_pipe")
(define_insn_reservation "niag2_imul" 5
- (and (eq_attr "cpu" "niagara2,niagara3")
+ (and (eq_attr "cpu" "niagara2")
(eq_attr "type" "imul"))
"niag2_pipe*5")
-(define_insn_reservation "niag2_idiv" 31
- (and (eq_attr "cpu" "niagara2,niagara3")
+(define_insn_reservation "niag3_imul" 9
+ (and (eq_attr "cpu" "niagara3")
+ (eq_attr "type" "imul"))
+ "niag2_pipe*9")
+
+(define_insn_reservation "niag2_idiv" 26
+ (and (eq_attr "cpu" "niagara2")
+ (eq_attr "type" "idiv"))
+ "niag2_pipe*26")
+
+(define_insn_reservation "niag3_idiv" 31
+ (and (eq_attr "cpu" "niagara3")
(eq_attr "type" "idiv"))
"niag2_pipe*31")
@@ -69,22 +79,42 @@
(eq_attr "type" "store,fpstore"))
"niag2_pipe")
-(define_insn_reservation "niag2_fp" 3
- (and (eq_attr "cpu" "niagara2,niagara3")
+(define_insn_reservation "niag2_fp" 6
+ (and (eq_attr "cpu" "niagara2")
(eq_attr "type" "fpmove,fpcmove,fpcrmove,fpcmp,fpmul"))
- "niag2_pipe*3")
+ "niag2_pipe*6")
+
+(define_insn_reservation "niag3_fp" 9
+ (and (eq_attr "cpu" "niagara3")
+ (eq_attr "type" "fpmove,fpcmove,fpcrmove,fpcmp,fpmul"))
+ "niag2_pipe*9")
(define_insn_reservation "niag2_fdivs" 19
- (and (eq_attr "cpu" "niagara2,niagara3")
+ (and (eq_attr "cpu" "niagara2")
(eq_attr "type" "fpdivs"))
"niag2_pipe*19")
+(define_insn_reservation "niag3_fdivs" 23
+ (and (eq_attr "cpu" "niagara3")
+ (eq_attr "type" "fpdivs"))
+ "niag2_pipe*23")
+
(define_insn_reservation "niag2_fdivd" 33
- (and (eq_attr "cpu" "niagara2,niagara3")
+ (and (eq_attr "cpu" "niagara2")
(eq_attr "type" "fpdivd"))
"niag2_pipe*33")
+(define_insn_reservation "niag3_fdivd" 37
+ (and (eq_attr "cpu" "niagara3")
+ (eq_attr "type" "fpdivd"))
+ "niag2_pipe*37")
+
(define_insn_reservation "niag2_vis" 6
- (and (eq_attr "cpu" "niagara2,niagara3")
+ (and (eq_attr "cpu" "niagara2")
(eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist,edge"))
"niag2_pipe*6")
+
+(define_insn_reservation "niag3_vis" 9
+ (and (eq_attr "cpu" "niagara3")
+ (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist,edge"))
+ "niag2_pipe*9")
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 7e124a0..6ccc97b 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -269,8 +269,32 @@ struct processor_costs niagara2_costs = {
COSTS_N_INSNS (5), /* imul */
COSTS_N_INSNS (5), /* imulX */
0, /* imul bit factor */
- COSTS_N_INSNS (31), /* idiv, average of 12 - 41 cycle range */
- COSTS_N_INSNS (31), /* idivX, average of 12 - 41 cycle range */
+ COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
+ COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
+ COSTS_N_INSNS (1), /* movcc/movr */
+ 0, /* shift penalty */
+};
+
+static const
+struct processor_costs niagara3_costs = {
+ COSTS_N_INSNS (3), /* int load */
+ COSTS_N_INSNS (3), /* int signed load */
+ COSTS_N_INSNS (3), /* int zeroed load */
+ COSTS_N_INSNS (3), /* float load */
+ COSTS_N_INSNS (9), /* fmov, fneg, fabs */
+ COSTS_N_INSNS (9), /* fadd, fsub */
+ COSTS_N_INSNS (9), /* fcmp */
+ COSTS_N_INSNS (9), /* fmov, fmovr */
+ COSTS_N_INSNS (9), /* fmul */
+ COSTS_N_INSNS (23), /* fdivs */
+ COSTS_N_INSNS (37), /* fdivd */
+ COSTS_N_INSNS (23), /* fsqrts */
+ COSTS_N_INSNS (37), /* fsqrtd */
+ COSTS_N_INSNS (9), /* imul */
+ COSTS_N_INSNS (9), /* imulX */
+ 0, /* imul bit factor */
+ COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
+ COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
COSTS_N_INSNS (1), /* movcc/movr */
0, /* shift penalty */
};
@@ -917,9 +941,11 @@ sparc_option_override (void)
sparc_costs = &niagara_costs;
break;
case PROCESSOR_NIAGARA2:
+ sparc_costs = &niagara2_costs;
+ break;
case PROCESSOR_NIAGARA3:
case PROCESSOR_NIAGARA4:
- sparc_costs = &niagara2_costs;
+ sparc_costs = &niagara3_costs;
break;
case PROCESSOR_NATIVE:
gcc_unreachable ();
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