[PATCH ARM] Fix PR50099

[Ramana Radhakrishnan]

Hi,

PR target/50099 is a case where we are using the wrong predicate for
the sign_extend from QI to DImode values. ldrsb has a lower range than
the other ldrb instructions in ARM state and hence one has to be
careful about generating the right addresses when splitting it.

Attached is a patch to fix this. I will commit this if there are no
regressions. A backport to 4.6 branch will be done after suitable
regression testing.

cheers
Ramana


2011-09-06  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>

	PR target/50099
	* config/arm/iterators.md (qhs_zextenddi_cstr): New.
	(qhs_zextenddi_op): New.
	* config/arm/arm.md ("zero_extend<mode>di2"): Use them.
        * config/arm/predicates.md ("arm_extendqisi_mem_op"):
Distinguish between ARM and Thumb2 states.

        PR target/50099
        * gcc.target/arm/pr50099.c: New test.
-------------- next part --------------
commit 9c268f1a74578ae082ea52dfcc655804b8319190
Author: Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
Date:   Tue Sep 6 15:14:14 2011 +0100

    Fix PR target/50099

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 40341bd..388254f 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -4163,8 +4163,8 @@
 
 (define_insn "zero_extend<mode>di2"
   [(set (match_operand:DI 0 "s_register_operand" "=r")
-        (zero_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>"
-					    "<qhs_extenddi_cstr>")))]
+        (zero_extend:DI (match_operand:QHSI 1 "<qhs_zextenddi_op>"
+					    "<qhs_zextenddi_cstr>")))]
   "TARGET_32BIT <qhs_zextenddi_cond>"
   "#"
   [(set_attr "length" "8")
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 219918c..da1f7af 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -390,10 +390,14 @@
 (define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
 (define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
 				      (QI "&& arm_arch6")])
-(define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
+(define_mode_attr qhs_zextenddi_op [(SI "s_register_operand")
 				   (HI "nonimmediate_operand")
 				   (QI "nonimmediate_operand")])
-(define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rm")])
+(define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
+				   (HI "nonimmediate_operand")
+				   (QI "arm_reg_or_extendqisi_mem_op")])
+(define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rUq")])
+(define_mode_attr qhs_zextenddi_cstr [(SI "r") (HI "rm") (QI "rm")])
 
 ;; Mode attributes used for fixed-point support.
 (define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16")
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index cfe8d33..50c1b43 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -296,8 +296,11 @@
 
 (define_special_predicate "arm_extendqisi_mem_op"
   (and (match_operand 0 "memory_operand")
-       (match_test "arm_legitimate_address_outer_p (mode, XEXP (op, 0),
-						    SIGN_EXTEND, 0)")))
+       (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode,
+                                                                 XEXP (op, 0),
+						                 SIGN_EXTEND,
+								 0)
+                               : memory_address_p (QImode, XEXP (op, 0))")))
 
 (define_special_predicate "arm_reg_or_extendqisi_mem_op"
   (ior (match_operand 0 "arm_extendqisi_mem_op")
diff --git a/gcc/testsuite/gcc.target/arm/pr50099.c b/gcc/testsuite/gcc.target/arm/pr50099.c
new file mode 100644
index 0000000..e767423
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr50099.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+
+typedef signed char int8_t ;
+typedef signed short int16_t;
+typedef signed long int32_t;
+typedef signed long long int64_t;
+
+int64_t foo (int8_t * arg)
+{
+  int64_t temp_1;
+
+  temp_1 = arg[256]; // index must be > 255 to ice!
+  return temp_1;
+}