[PATCH RFC] Sparc vector mode segregation

Eric Botcazou ebotcazou@adacore.com
Mon Oct 17 22:34:00 GMT 2011

> This is an implementation of the changes I spoke about the other
> week.  These changes segregate the vector vs. non-vector mode
> handling in the sparc backend.

I think that the original motivation for the previous design was the 32-bit 
vector ABI, where the arguments are passed in integer registers.  So for:

typedef char  vec8 __attribute__((vector_size(8)));

extern vec8 foo (vec8);

vec8 bar(vec8 a, vec8 b)
  return foo(a & b);

the generated code at -O2 is optimal:

	and	%o2, %o0, %o0
	sethi	%hi(foo), %g1
	jmp	%g1 + %lo(foo)
	 and	%o3, %o1, %o1

My understand is that, with the changes, you will spill and reload twice.
Of course things are totally different with the 64-bit ABI.

A compromise could be to segregate the patterns, but still have alternatives 
for the other registers, i.e. andsi3 would still have the 'd' alternative at 
the end and the andv1si3 would have a 'r' alternative at the end, them being 
disparaged properly.

> In fact, gcc.target/sparc/combined-1.c passes always even without
> adjusting the optimization level to placate the register allocator
> and many tests now generate more VIS instructions than before,
> particularly on 32-bit.

Feel free to revert the adjustment I made as part of the patch.

Eric Botcazou

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