New port^2: Renesas RL78
DJ Delorie
dj@redhat.com
Tue Nov 22 04:02:00 GMT 2011
> "rl" > "rs", mind sorting this in?
Oops. I'd been putting RL78 before RX for so long it seemed natural
(it's been powerpc so far, which doesn't come between rl78 and rx)
> > Index: gcc/doc/extend.texi
> > ===================================================================
> > -the SPU and M32C targets support other address spaces. On the SPU target, for
> > +the SPU, M32C, and RL78 targets support other address spaces. On the SPU target, for
>
> Mind the long line.
Reformatted (which is what I was trying to avoid, since now the patch
touches every line in that paragraph)
> > +On the RL78 target, variables qualified with @code{__far} are accessed
> > +with 32-bit pointers (20 bit addresses) rather than the default 16-bit
>
> "20-bit"
Fixed.
> > +addresses. Non-far variables are assumed to appear in the topmost 64K
> > +of the address space.
>
> I suggest to explicitly refer to kB or kb (byte or bit) perhaps?
"64 kB" then.
> Same note on sorting as above. :-)
Same fix.
> > +@node RL78 Options
> > +@subsection RL78 Options
> > +@cindex RL78 Options
>
> Ditto.
Ditto.
> > +@item -msim
> > +@opindex msim
> > +Link in additional target libraries to support operation within a
> > +simulator.
>
> "Link", versus...
>
> > +@item -mmul=none
> > +@itemx -mmul=g13
> > +@itemx -mmul=rl78
> > +@opindex mmul
> > +Selects the type of hardware multiplication support desired.
>
> ..."Selects" feels a bit inconsistent, though I can also see the
> argument where "link" is what the program does, whereas "select"
> is what the user does.
I changed Link to Links, and rewrote the "Selects" line. It looked
like the descriptions are what the options do, not what the user or
gcc does.
> Really 1..7, not 0..7? That's unexpected and a bit inconsistent
> with Int8.
Yes, really 1..7. It's for shift counts, and they're hard-coded in
the insn (i.e. there are 7 shl insns, 7 shr insns...). The bit
pattern that would be "a shift of zero" translates into a completely
different insn.
> (Reading through this, some very fond memories of the Z80 come up
> in my memories. :-)
My first "owned" computer was a Z80-based Sinclair ZX81 :-)
> Don't you want to mention your name there? I would find that
> appropriate.
It's not what we typically have done with Red Hat ports.
> Do you consider the links from install.texi important? Keep them if
> you do, in general we try to minimize those (and keep them in
> readings.html where you have added the same links).
No, I was just following the RX entry.
> All .texi and .html changes are okay, modulo the notes above.
Updated patches for just docs and www attached.
Index: MAINTAINERS
===================================================================
--- MAINTAINERS (revision 181596)
+++ MAINTAINERS (working copy)
@@ -84,12 +84,13 @@ mmix port Hans-Peter Nilsson hp@bitrang
mn10300 port Jeff Law law@redhat.com
mn10300 port Alexandre Oliva aoliva@redhat.com
moxie port Anthony Green green@moxielogic.com
pdp11 port Paul Koning ni1d@arrl.net
picochip port Hariharan Sandanagobalane hariharan@picochip.com
picochip port Daniel Towner dant@picochip.com
+rl78 port DJ Delorie dj@redhat.com
rs6000 port Geoff Keating geoffk@geoffk.org
rs6000 port David Edelsohn dje.gcc@gmail.com
rs6000 vector extns Aldy Hernandez aldyh@redhat.com
rx port Nick Clifton nickc@redhat.com
s390 port Hartmut Penner hpenner@de.ibm.com
s390 port Ulrich Weigand uweigand@de.ibm.com
Index: gcc/doc/extend.texi
===================================================================
--- gcc/doc/extend.texi (revision 181596)
+++ gcc/doc/extend.texi (working copy)
@@ -1217,17 +1217,18 @@ Fixed-point types are supported by the D
@node Named Address Spaces
@section Named address spaces
@cindex named address spaces
As an extension, the GNU C compiler supports named address spaces as
defined in the N1275 draft of ISO/IEC DTR 18037. Support for named
-address spaces in GCC will evolve as the draft technical report changes.
-Calling conventions for any target might also change. At present, only
-the SPU and M32C targets support other address spaces. On the SPU target, for
-example, variables may be declared as belonging to another address space
-by qualifying the type with the @code{__ea} address space identifier:
+address spaces in GCC will evolve as the draft technical report
+changes. Calling conventions for any target might also change. At
+present, only the SPU, M32C, and RL78 targets support other address
+spaces. On the SPU target, for example, variables may be declared as
+belonging to another address space by qualifying the type with the
+@code{__ea} address space identifier:
@smallexample
extern int __ea i;
@end smallexample
When the variable @code{i} is accessed, the compiler will generate
@@ -1241,12 +1242,17 @@ document for more details.
On the M32C target, with the R8C and M16C cpu variants, variables
qualified with @code{__far} are accessed using 32-bit addresses in
order to access memory beyond the first 64k bytes. If @code{__far} is
used with the M32CM or M32C cpu variants, it has no effect.
+On the RL78 target, variables qualified with @code{__far} are accessed
+with 32-bit pointers (20-bit addresses) rather than the default 16-bit
+addresses. Non-far variables are assumed to appear in the topmost 64
+kB of the address space.
+
@node Zero Length
@section Arrays of Length Zero
@cindex arrays of length zero
@cindex zero-length arrays
@cindex length-zero arrays
@cindex flexible array members
@@ -2550,13 +2556,13 @@ then be sure to write this declaration i
This attribute is ignored for R8C target.
@item interrupt
@cindex interrupt handler functions
Use this attribute on the ARM, AVR, Epiphany, M32C, M32R/D, m68k, MeP, MIPS,
-RX and Xstormy16 ports to indicate that the specified function is an
+RL78, RX and Xstormy16 ports to indicate that the specified function is an
interrupt handler. The compiler will generate function entry and exit
sequences suitable for use in an interrupt handler when this attribute
is present.
Note, interrupt handlers for the Blackfin, H8/300, H8/300H, H8S, MicroBlaze,
and SH processors can be specified via the @code{interrupt_handler} attribute.
@@ -2608,12 +2614,16 @@ void __attribute__ ((interrupt, keep_int
use_debug_exception_return)) v6 ();
void __attribute__ ((interrupt, use_shadow_register_set,
keep_interrupts_masked,
use_debug_exception_return)) v7 ();
@end smallexample
+On RL78, use @code{brk_interrupt} instead of @code{interrupt} for
+handlers intended to be used with the @code{BRK} opcode (i.e. those
+that must end with @code{RETB} instead of @code{RETI}).
+
@item ifunc ("@var{resolver}")
@cindex @code{ifunc} attribute
The @code{ifunc} attribute is used to mark a function as an indirect
function using the STT_GNU_IFUNC symbol type extension to the ELF
standard. This allows the resolution of the symbol value to be
determined dynamically at load time, and an optimized version of the
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi (revision 181596)
+++ gcc/doc/invoke.texi (working copy)
@@ -775,12 +775,15 @@ Objective-C and Objective-C++ Dialects}.
@gccoptlist{-mae=@var{ae_type} -mvliw-lookahead=@var{N} @gol
-msymbol-as-address -mno-inefficient-warnings}
@emph{PowerPC Options}
See RS/6000 and PowerPC Options.
+@emph{RL78 Options}
+@gccoptlist{-msim -mmul=none -mmul=g13 -mmul=rl78}
+
@emph{RS/6000 and PowerPC Options}
@gccoptlist{-mcpu=@var{cpu-type} @gol
-mtune=@var{cpu-type} @gol
-mcmodel=@var{code-model} @gol
-mpower -mno-power -mpower2 -mno-power2 @gol
-mpowerpc -mpowerpc64 -mno-powerpc @gol
@@ -10297,12 +10300,13 @@ platform.
* MIPS Options::
* MMIX Options::
* MN10300 Options::
* PDP-11 Options::
* picoChip Options::
* PowerPC Options::
+* RL78 Options::
* RS/6000 and PowerPC Options::
* RX Options::
* S/390 and zSeries Options::
* Score Options::
* SH Options::
* Solaris 2 Options::
@@ -15925,12 +15929,35 @@ the warning to be turned off.
@node PowerPC Options
@subsection PowerPC Options
@cindex PowerPC options
These are listed under @xref{RS/6000 and PowerPC Options}.
+@node RL78 Options
+@subsection RL78 Options
+@cindex RL78 Options
+
+@table @gcctabopt
+
+@item -msim
+@opindex msim
+Links in additional target libraries to support operation within a
+simulator.
+
+@item -mmul=none
+@itemx -mmul=g13
+@itemx -mmul=rl78
+@opindex mmul
+Specifies the type of hardware multiplication support desired. The
+default is @code{none}, which uses software multiplication functions.
+The @code{g13} option is for the hardware multiply/divide peripheral
+only on the RL78/G13 targets. The @code{rl78} option is for the
+standard hardware multiplication defined in the RL78 software manual.
+
+@end table
+
@node RS/6000 and PowerPC Options
@subsection IBM RS/6000 and PowerPC Options
@cindex RS/6000 and PowerPC Options
@cindex IBM RS/6000 and PowerPC Options
These @samp{-m} options are defined for the IBM RS/6000 and PowerPC:
Index: gcc/doc/contrib.texi
===================================================================
--- gcc/doc/contrib.texi (revision 181596)
+++ gcc/doc/contrib.texi (working copy)
@@ -213,13 +213,13 @@ Bud Davis for work on the G77 and GNU Fo
@item
Mo DeJong for GCJ and libgcj bug fixes.
@item
DJ Delorie for the DJGPP port, build and libiberty maintenance,
-various bug fixes, and the M32C and MeP ports.
+various bug fixes, and the M32C, MeP, and RL78 ports.
@item
Arnaud Desitter for helping to debug GNU Fortran.
@item
Gabriel Dos Reis for contributions to G++, contributions and
Index: gcc/doc/md.texi
===================================================================
--- gcc/doc/md.texi (revision 181596)
+++ gcc/doc/md.texi (working copy)
@@ -2976,12 +2976,102 @@ offset) after the opcode.
@item R
A memory reference that is encoded within the opcode.
@end table
+@item RL78---@file{config/rl78/constraints.md}
+@table @code
+
+@item Int3
+An integer constant in the range 1 @dots{} 7.
+@item Int8
+An integer constant in the range 0 @dots{} 255.
+@item J
+An integer constant in the range @minus{}255 @dots{} 0
+@item K
+The integer constant 1.
+@item L
+The integer constant -1.
+@item M
+The integer constant 0.
+@item N
+The integer constant 2.
+@item O
+The integer constant -2.
+@item P
+An integer constant in the range 1 @dots{} 15.
+@item Qbi
+The built-in compare types--eq, ne, gtu, ltu, geu, and leu.
+@item Qsc
+The synthetic compare types--gt, lt, ge, and le.
+@item Wab
+A memory reference with an absolute address.
+@item Wbc
+A memory reference using @code{BC} as a base register, with an optional offset.
+@item Wca
+A memory reference using @code{AX}, @code{BC}, @code{DE}, or @code{HL} for the address, for calls.
+@item Wcv
+A memory reference using any 16-bit register pair for the address, for calls.
+@item Wd2
+A memory reference using @code{DE} as a base register, with an optional offset.
+@item Wde
+A memory reference using @code{DE} as a base register, without any offset.
+@item Wfr
+Any memory reference to an address in the far address space.
+@item Wh1
+A memory reference using @code{HL} as a base register, with an optional one-byte offset.
+@item Whb
+A memory reference using @code{HL} as a base register, with @code{B} or @code{C} as the index register.
+@item Whl
+A memory reference using @code{HL} as a base register, without any offset.
+@item Ws1
+A memory reference using @code{SP} as a base register, with an optional one-byte offset.
+@item Y
+Any memory reference to an address in the near address space.
+@item A
+The @code{AX} register.
+@item B
+The @code{BC} register.
+@item D
+The @code{DE} register.
+@item R
+@code{A} through @code{L} registers.
+@item S
+The @code{SP} register.
+@item T
+The @code{HL} register.
+@item Z08W
+The 16-bit @code{R8} register.
+@item Z10W
+The 16-bit @code{R10} register.
+@item Zint
+The registers reserved for interrupts (@code{R24} to @code{R31}).
+@item a
+The @code{A} register.
+@item b
+The @code{B} register.
+@item c
+The @code{C} register.
+@item d
+The @code{D} register.
+@item e
+The @code{E} register.
+@item h
+The @code{H} register.
+@item l
+The @code{L} register.
+@item v
+The virtual registers.
+@item w
+The @code{PSW} register.
+@item x
+The @code{X} register.
+
+@end table
+
@item RX---@file{config/rx/constraints.md}
@table @code
@item Q
An address which does not involve register indirect addressing or
pre/post increment/decrement addressing.
Index: gcc/doc/install.texi
===================================================================
--- gcc/doc/install.texi (revision 181596)
+++ gcc/doc/install.texi (working copy)
@@ -4138,12 +4138,19 @@ the PSIM simulator.
@heading @anchor{powerpcle-x-eabi}powerpcle-*-eabi
Embedded PowerPC system in little endian mode.
@html
<hr />
@end html
+@heading @anchor{rl78-x-elf}rl78-*-elf
+The Renesas RL78 processor.
+This configuration is intended for embedded systems.
+
+@html
+<hr />
+@end html
@heading @anchor{rx-x-elf}rx-*-elf
The Renesas RX processor. See
@uref{http://eu.renesas.com/fmwk.jsp?cnt=rx600_series_landing.jsp&fp=/products/mpumcu/rx_family/rx600_series}
for more information about this processor.
@html
Index: htdocs/backends.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/backends.html,v
retrieving revision 1.42
diff -p -U5 -r1.42 backends.html
--- htdocs/backends.html 5 Nov 2011 20:55:57 -0000 1.42
+++ htdocs/backends.html 22 Nov 2011 00:58:19 -0000
@@ -91,10 +91,11 @@ mips | Q CB qr p bda s
mmix | HM Q C q p b a e
mn10300 | ?? c g s
ms1 | S F B p g bd
pa | ? Q CBD qr m da e
pdp11 | L IC qrcp e
+rl78 | L F l p gmb s
rs6000 | Q C qr da
s390 | ? Q qr p g bda e
sh | Q CB qr da
sparc | Q CB qr p da
spu | ? Q *C p g bd
Index: htdocs/index.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/index.html,v
retrieving revision 1.827
diff -p -U5 -r1.827 index.html
--- htdocs/index.html 21 Nov 2011 15:19:08 -0000 1.827
+++ htdocs/index.html 22 Nov 2011 00:58:19 -0000
@@ -51,10 +51,15 @@ mission statement</a>.</p>
<h2 style="margin-top:0pt;" id="news">News</h2>
<dl class="news">
+<dt><span>Renesas RL78 processor support</span>
+ <span class="date">[2011-11-21]</span></dt>
+<dd>A port for the Renesas RL78 family of processors has been contributed by
+Red Hat.</dd>
+
<dt><span>Transactional memory support</span>
<span class="date">[2011-11-15]</span></dt>
<dd>An implementation of the
ongoing <a href="http://gcc.gnu.org/wiki/TransactionalMemory">transactional
memory</a> standard has been added. Code was contributed by Richard
Index: htdocs/readings.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/readings.html,v
retrieving revision 1.216
diff -p -U5 -r1.216 readings.html
--- htdocs/readings.html 5 Nov 2011 20:55:57 -0000 1.216
+++ htdocs/readings.html 22 Nov 2011 00:58:19 -0000
@@ -243,10 +243,15 @@ Intel®64 and IA-32 Architectures Sof
<br /><a href="http://publib16.boulder.ibm.com/pseries/en_US/infocenter/base/43_docs/aixassem/alangref/toc.htm">AIX V4.3 Assembler Language Ref.</a>
<br /><a href="http://publibn.boulder.ibm.com/doc_link/en_US/a_doc_lib/aixassem/alangref/alangreftfrm.htm">AIX 5L Assembler Language Ref.</a>
<br /><a href="http://www.power.org/resources/downloads/">Documentation and tools at power.org</a>
</li>
+ <li>rl78
+ <br />Manufacturer: Renesas
+ <br /><a href="http://www.renesas.com/pr/mcu/rl78/">Renesas RL78 Processors</a>
+ </li>
+
<li>rx
<br />Manufacturer: Renesas
<br /><a href="http://documentation.renesas.com/eng/products/mpumcu/rej09b0460_rx610hm.pdf">RX610 Hardware Manual</a>
</li>
More information about the Gcc-patches
mailing list