[PATCH, i386]: Move unspec/unspecv constants around
Uros Bizjak
ubizjak@gmail.com
Mon Nov 21 19:06:00 GMT 2011
Hello!
This patch moves unspec/unspecv constants to their new homes. The
patch also moves a couple of fence patterns from sse.md to sync.md.
No functional changes.
2011-11-21 Uros Bizjak <ubizjak@gmail.com>
* config/i386/mmx.md (unspec) <UNSPEC_MOVNTQ, UNSPEC_PFRCP,
UNSPEC_PFRCPIT1, UNSPEC_PFRCPIT2, UNSPEC_PFRSQRT, UNSPEC_PFRSQIT1>:
Move from config/i386/i386.md
(unspecv) <UNSPECV_EMMS, UNSPECV_FEMMS>: Ditto.
* config/i386/sse.md (unspec) <UNSPEC_MOVNT,UNSPEC_MOVU, UNSPEC_LDDQU,
UNSPEC_PSHUFB, UNSPEC_PSIGN, UNSPEC_PALIGNR, UNSPEC_EXTRQI,
UNSPEC_EXTRQ, UNSPEC_INSERTQI, UNSPEC_INSERTQ, UNSPEC_BLENDV,
UNSPEC_INSERTPS, UNSPEC_DP, UNSPEC_MOVNTDQA, UNSPEC_MPSADBW,
UNSPEC_PHMINPOSUW, UNSPEC_PTEST, UNSPEC_PCMPESTR, UNSPEC_PCMPISTR,
UNSPEC_FMADDSUB, UNSPEC_XOP_UNSIGNED_CMP, UNSPEC_XOP_TRUEFALSE,
UNSPEC_XOP_PERMUTE, UNSPEC_FRCZ, UNSPEC_AESENC, UNSPEC_AESENCLAST,
UNSPEC_AESDEC, UNSPEC_AESDECLAST, UNSPEC_AESIMC,
UNSPEC_AESKEYGENASSIST, UNSPEC_PCLMUL, UNSPEC_PCMP, UNSPEC_VPERMIL,
UNSPEC_VPERMIL2, UNSPEC_VPERMIL2F128, UNSPEC_CAST, UNSPEC_VTESTP,
UNSPEC_VCVTPH2PS, UNSPEC_VCVTPS2PH, UNSPEC_VPERMSI, UNSPEC_VPERMDF,
UNSPEC_VPERMSF, UNSPEC_VPERMTI, UNSPEC_GATHER, UNSPEC_VSIBADDR>: Ditto.
(unspecv) <UNSPECV_LDMXCSR, UNSPECV_STMXCSR, UNSPECV_CLFLUSH,
UNSPECV_MONITOR, UNSPECV_MWAIT, UNSPECV_VZEROALL, UNSPECV_VZEROUPPER>:
Ditto.
* config/i386/sync.md (unspec) <UNSPEC_LFENCE, UNSPEC_SFENCE,
UNSPEC_MFENCE, UNSPEC_MOVA>: Ditto.
(unspecv) <UNSPECV_CMPXCHG_1, UNSPECV_CMPXCHG_2, UNSPECV_CMPXCHG_3,
UNSPECV_CMPXCHG_4, UNSPECV_XCHG, UNSPECV_LOCK>: Ditto.
(sse2_lfence): Move from config/i386/sse.md.
(*sse2_lfence): Ditto.
(sse_sfence): Ditto.
(*sse_sfence): Ditto.
(sse2_mfence): Ditto.
(mfence_sse2): Ditto. Rename from *sse2_mfence. Enable also for TARGET_64BIT.
(mem_thread_fence): Use mfence_sse2.
Tested on x86_64-pc-linux-gnu{,-m32} and committed to mainline SVN.
Uros.
-------------- next part --------------
Index: i386.md
===================================================================
--- i386.md (revision 181585)
+++ i386.md (working copy)
@@ -62,8 +62,6 @@
;; ; -- print a semicolon (after prefixes due to bug in older gas).
;; @ -- print a segment register of thread base pointer load
-;; UNSPEC usage:
-
(define_c_enum "unspec" [
;; Relocation specifiers
UNSPEC_GOT
@@ -108,6 +106,7 @@
UNSPEC_LD_MPIC ; load_macho_picbase
UNSPEC_TRUNC_NOOP
UNSPEC_DIV_ALREADY_SPLIT
+ UNSPEC_MS_TO_SYSV_CALL
UNSPEC_CALL_NEEDS_VZEROUPPER
UNSPEC_PAUSE
@@ -115,22 +114,9 @@
UNSPEC_FIX_NOTRUNC
UNSPEC_MASKMOV
UNSPEC_MOVMSK
- UNSPEC_MOVNTQ
- UNSPEC_MOVNT
- UNSPEC_MOVU
UNSPEC_RCP
UNSPEC_RSQRT
- UNSPEC_SFENCE
- UNSPEC_PFRCP
- UNSPEC_PFRCPIT1
- UNSPEC_PFRCPIT2
- UNSPEC_PFRSQRT
- UNSPEC_PFRSQIT1
- UNSPEC_MFENCE
- UNSPEC_LFENCE
UNSPEC_PSADBW
- UNSPEC_LDDQU
- UNSPEC_MS_TO_SYSV_CALL
;; Generic math support
UNSPEC_COPYSIGN
@@ -178,105 +164,32 @@
UNSPEC_SP_TLS_SET
UNSPEC_SP_TLS_TEST
- ;; SSSE3
- UNSPEC_PSHUFB
- UNSPEC_PSIGN
- UNSPEC_PALIGNR
-
- ;; For SSE4A support
- UNSPEC_EXTRQI
- UNSPEC_EXTRQ
- UNSPEC_INSERTQI
- UNSPEC_INSERTQ
-
- ;; For SSE4.1 support
- UNSPEC_BLENDV
- UNSPEC_INSERTPS
- UNSPEC_DP
- UNSPEC_MOVNTDQA
- UNSPEC_MPSADBW
- UNSPEC_PHMINPOSUW
- UNSPEC_PTEST
+ ;; For ROUND support
UNSPEC_ROUND
- ;; For SSE4.2 support
+ ;; For CRC32 support
UNSPEC_CRC32
- UNSPEC_PCMPESTR
- UNSPEC_PCMPISTR
- ;; For FMA4 support
- UNSPEC_FMADDSUB
- UNSPEC_XOP_UNSIGNED_CMP
- UNSPEC_XOP_TRUEFALSE
- UNSPEC_XOP_PERMUTE
- UNSPEC_FRCZ
+ ;; For RDRAND support
+ UNSPEC_RDRAND
- ;; For AES support
- UNSPEC_AESENC
- UNSPEC_AESENCLAST
- UNSPEC_AESDEC
- UNSPEC_AESDECLAST
- UNSPEC_AESIMC
- UNSPEC_AESKEYGENASSIST
-
- ;; For PCLMUL support
- UNSPEC_PCLMUL
-
- ;; For AVX support
- UNSPEC_PCMP
- UNSPEC_VPERMIL
- UNSPEC_VPERMIL2
- UNSPEC_VPERMIL2F128
- UNSPEC_CAST
- UNSPEC_VTESTP
- UNSPEC_VCVTPH2PS
- UNSPEC_VCVTPS2PH
-
- ;; For AVX2 support
- UNSPEC_VPERMSI
- UNSPEC_VPERMDF
- UNSPEC_VPERMSF
- UNSPEC_VPERMTI
- UNSPEC_GATHER
- UNSPEC_VSIBADDR
-
;; For BMI support
UNSPEC_BEXTR
- ;; For RDRAND support
- UNSPEC_RDRAND
-
;; For BMI2 support
UNSPEC_PDEP
UNSPEC_PEXT
-
- ;; For __atomic support
- UNSPEC_MOVA
])
(define_c_enum "unspecv" [
UNSPECV_BLOCKAGE
UNSPECV_STACK_PROBE
UNSPECV_PROBE_STACK_RANGE
- UNSPECV_EMMS
- UNSPECV_LDMXCSR
- UNSPECV_STMXCSR
- UNSPECV_FEMMS
- UNSPECV_CLFLUSH
UNSPECV_ALIGN
- UNSPECV_MONITOR
- UNSPECV_MWAIT
- UNSPECV_CMPXCHG_1
- UNSPECV_CMPXCHG_2
- UNSPECV_CMPXCHG_3
- UNSPECV_CMPXCHG_4
- UNSPECV_XCHG
- UNSPECV_LOCK
UNSPECV_PROLOGUE_USE
+ UNSPECV_SPLIT_STACK_RETURN
UNSPECV_CLD
UNSPECV_NOPS
- UNSPECV_VZEROALL
- UNSPECV_VZEROUPPER
UNSPECV_RDTSC
UNSPECV_RDTSCP
UNSPECV_RDPMC
@@ -288,7 +201,6 @@
UNSPECV_RDGSBASE
UNSPECV_WRFSBASE
UNSPECV_WRGSBASE
- UNSPECV_SPLIT_STACK_RETURN
])
;; Constants to represent rounding modes in the ROUND instruction
Index: mmx.md
===================================================================
--- mmx.md (revision 181585)
+++ mmx.md (working copy)
@@ -30,6 +30,20 @@
;; means that we should never use any of these patterns except at the
;; direction of the user via a builtin.
+(define_c_enum "unspec" [
+ UNSPEC_MOVNTQ
+ UNSPEC_PFRCP
+ UNSPEC_PFRCPIT1
+ UNSPEC_PFRCPIT2
+ UNSPEC_PFRSQRT
+ UNSPEC_PFRSQIT1
+])
+
+(define_c_enum "unspecv" [
+ UNSPECV_EMMS
+ UNSPECV_FEMMS
+])
+
;; 8 byte integral modes handled by MMX (and by extension, SSE)
(define_mode_iterator MMXMODEI [V8QI V4HI V2SI])
(define_mode_iterator MMXMODEI8 [V8QI V4HI V2SI V1DI])
Index: sse.md
===================================================================
--- sse.md (revision 181585)
+++ sse.md (working copy)
@@ -18,6 +18,85 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
+(define_c_enum "unspec" [
+ ;; SSE
+ UNSPEC_MOVNT
+ UNSPEC_MOVU
+
+ ;; SSE3
+ UNSPEC_LDDQU
+
+ ;; SSSE3
+ UNSPEC_PSHUFB
+ UNSPEC_PSIGN
+ UNSPEC_PALIGNR
+
+ ;; For SSE4A support
+ UNSPEC_EXTRQI
+ UNSPEC_EXTRQ
+ UNSPEC_INSERTQI
+ UNSPEC_INSERTQ
+
+ ;; For SSE4.1 support
+ UNSPEC_BLENDV
+ UNSPEC_INSERTPS
+ UNSPEC_DP
+ UNSPEC_MOVNTDQA
+ UNSPEC_MPSADBW
+ UNSPEC_PHMINPOSUW
+ UNSPEC_PTEST
+
+ ;; For SSE4.2 support
+ UNSPEC_PCMPESTR
+ UNSPEC_PCMPISTR
+
+ ;; For FMA4 support
+ UNSPEC_FMADDSUB
+ UNSPEC_XOP_UNSIGNED_CMP
+ UNSPEC_XOP_TRUEFALSE
+ UNSPEC_XOP_PERMUTE
+ UNSPEC_FRCZ
+
+ ;; For AES support
+ UNSPEC_AESENC
+ UNSPEC_AESENCLAST
+ UNSPEC_AESDEC
+ UNSPEC_AESDECLAST
+ UNSPEC_AESIMC
+ UNSPEC_AESKEYGENASSIST
+
+ ;; For PCLMUL support
+ UNSPEC_PCLMUL
+
+ ;; For AVX support
+ UNSPEC_PCMP
+ UNSPEC_VPERMIL
+ UNSPEC_VPERMIL2
+ UNSPEC_VPERMIL2F128
+ UNSPEC_CAST
+ UNSPEC_VTESTP
+ UNSPEC_VCVTPH2PS
+ UNSPEC_VCVTPS2PH
+
+ ;; For AVX2 support
+ UNSPEC_VPERMSI
+ UNSPEC_VPERMDF
+ UNSPEC_VPERMSF
+ UNSPEC_VPERMTI
+ UNSPEC_GATHER
+ UNSPEC_VSIBADDR
+])
+
+(define_c_enum "unspecv" [
+ UNSPECV_LDMXCSR
+ UNSPECV_STMXCSR
+ UNSPECV_CLFLUSH
+ UNSPECV_MONITOR
+ UNSPECV_MWAIT
+ UNSPECV_VZEROALL
+ UNSPECV_VZEROUPPER
+])
+
;; All vector modes including V?TImode, used in move patterns.
(define_mode_iterator V16
[(V32QI "TARGET_AVX") V16QI
@@ -8041,25 +8120,6 @@
(set_attr "prefix" "maybe_vex")
(set_attr "memory" "store")])
-(define_expand "sse_sfence"
- [(set (match_dup 0)
- (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
- "TARGET_SSE || TARGET_3DNOW_A"
-{
- operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
- MEM_VOLATILE_P (operands[0]) = 1;
-})
-
-(define_insn "*sse_sfence"
- [(set (match_operand:BLK 0 "" "")
- (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
- "TARGET_SSE || TARGET_3DNOW_A"
- "sfence"
- [(set_attr "type" "sse")
- (set_attr "length_address" "0")
- (set_attr "atom_sse_attr" "fence")
- (set_attr "memory" "unknown")])
-
(define_insn "sse2_clflush"
[(unspec_volatile [(match_operand 0 "address_operand" "p")]
UNSPECV_CLFLUSH)]
@@ -8069,44 +8129,7 @@
(set_attr "atom_sse_attr" "fence")
(set_attr "memory" "unknown")])
-(define_expand "sse2_mfence"
- [(set (match_dup 0)
- (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
- "TARGET_SSE2"
-{
- operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
- MEM_VOLATILE_P (operands[0]) = 1;
-})
-(define_insn "*sse2_mfence"
- [(set (match_operand:BLK 0 "" "")
- (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
- "TARGET_64BIT || TARGET_SSE2"
- "mfence"
- [(set_attr "type" "sse")
- (set_attr "length_address" "0")
- (set_attr "atom_sse_attr" "fence")
- (set_attr "memory" "unknown")])
-
-(define_expand "sse2_lfence"
- [(set (match_dup 0)
- (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
- "TARGET_SSE2"
-{
- operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
- MEM_VOLATILE_P (operands[0]) = 1;
-})
-
-(define_insn "*sse2_lfence"
- [(set (match_operand:BLK 0 "" "")
- (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
- "TARGET_SSE2"
- "lfence"
- [(set_attr "type" "sse")
- (set_attr "length_address" "0")
- (set_attr "atom_sse_attr" "lfence")
- (set_attr "memory" "unknown")])
-
(define_insn "sse3_mwait"
[(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
(match_operand:SI 1 "register_operand" "c")]
Index: sync.md
===================================================================
--- sync.md (revision 181585)
+++ sync.md (working copy)
@@ -18,34 +18,111 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
+(define_c_enum "unspec" [
+ UNSPEC_LFENCE
+ UNSPEC_SFENCE
+ UNSPEC_MFENCE
+ UNSPEC_MOVA ; For __atomic support
+])
+
+(define_c_enum "unspecv" [
+ UNSPECV_CMPXCHG_1
+ UNSPECV_CMPXCHG_2
+ UNSPECV_CMPXCHG_3
+ UNSPECV_CMPXCHG_4
+ UNSPECV_XCHG
+ UNSPECV_LOCK
+])
+
+(define_expand "sse2_lfence"
+ [(set (match_dup 0)
+ (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
+ "TARGET_SSE2"
+{
+ operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+ MEM_VOLATILE_P (operands[0]) = 1;
+})
+
+(define_insn "*sse2_lfence"
+ [(set (match_operand:BLK 0 "" "")
+ (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
+ "TARGET_SSE2"
+ "lfence"
+ [(set_attr "type" "sse")
+ (set_attr "length_address" "0")
+ (set_attr "atom_sse_attr" "lfence")
+ (set_attr "memory" "unknown")])
+
+(define_expand "sse_sfence"
+ [(set (match_dup 0)
+ (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
+ "TARGET_SSE || TARGET_3DNOW_A"
+{
+ operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+ MEM_VOLATILE_P (operands[0]) = 1;
+})
+
+(define_insn "*sse_sfence"
+ [(set (match_operand:BLK 0 "" "")
+ (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
+ "TARGET_SSE || TARGET_3DNOW_A"
+ "sfence"
+ [(set_attr "type" "sse")
+ (set_attr "length_address" "0")
+ (set_attr "atom_sse_attr" "fence")
+ (set_attr "memory" "unknown")])
+
+(define_expand "sse2_mfence"
+ [(set (match_dup 0)
+ (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
+ "TARGET_SSE2"
+{
+ operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+ MEM_VOLATILE_P (operands[0]) = 1;
+})
+
+(define_insn "mfence_sse2"
+ [(set (match_operand:BLK 0 "" "")
+ (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
+ "TARGET_64BIT || TARGET_SSE2"
+ "mfence"
+ [(set_attr "type" "sse")
+ (set_attr "length_address" "0")
+ (set_attr "atom_sse_attr" "fence")
+ (set_attr "memory" "unknown")])
+
+(define_insn "mfence_nosse"
+ [(set (match_operand:BLK 0 "" "")
+ (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))
+ (clobber (reg:CC FLAGS_REG))]
+ "!(TARGET_64BIT || TARGET_SSE2)"
+ "lock{%;} or{l}\t{$0, (%%esp)|DWORD PTR [esp], 0}"
+ [(set_attr "memory" "unknown")])
+
(define_expand "mem_thread_fence"
[(match_operand:SI 0 "const_int_operand" "")] ;; model
""
{
/* Unless this is a SEQ_CST fence, the i386 memory model is strong
enough not to require barriers of any kind. */
- if (INTVAL (operands[0]) != MEMMODEL_SEQ_CST)
- DONE;
+ if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST)
+ {
+ rtx (*mfence_insn)(rtx);
+ rtx mem;
- if (TARGET_64BIT || TARGET_SSE2)
- emit_insn (gen_sse2_mfence ());
- else
- {
- rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+ if (TARGET_64BIT || TARGET_SSE2)
+ mfence_insn = gen_mfence_sse2;
+ else
+ mfence_insn = gen_mfence_nosse;
+
+ mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
MEM_VOLATILE_P (mem) = 1;
- emit_insn (gen_mfence_nosse (mem));
+
+ emit_insn (mfence_insn (mem));
}
DONE;
})
-(define_insn "mfence_nosse"
- [(set (match_operand:BLK 0 "" "")
- (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))
- (clobber (reg:CC FLAGS_REG))]
- "!(TARGET_64BIT || TARGET_SSE2)"
- "lock{%;} or{l}\t{$0, (%%esp)|DWORD PTR [esp], 0}"
- [(set_attr "memory" "unknown")])
-
;; ??? From volume 3 section 7.1.1 Guaranteed Atomic Operations,
;; Only beginning at Pentium family processors do we get any guarantee of
;; atomicity in aligned 64-bit quantities. Beginning at P6, we get a
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