[lra] patch rewriting inheritance and speeding LRA up

[Vladimir Makarov]

The following patch contains a major rewriting inheritance code to 
permit inheritance from non-reload insns.  That is important for targets 
(like x86-64) permitting memory in general insns and as a result 
considerably decreasing code size.  Now LRA can do the following 
transformations:

      p <- ...             i <- ...
      ...                  p <- i    (new insn)
      ...             =>
<- ... p ... <- ... i ...
    or
      ...                  i <- p    (new insn)
<- ... p ... <- ... i ...
      ...             =>
<- ... p ... <- ... i ...

where p is spilled original pseudo and i is a new inheritance pseudo.

The patch fixes inheritance code to update debug info and liveness info 
correctly.

The patch also speeds LRA up by doing mem-mem coalescing and creating 
live ranges less frequently only when it is really needed.

And finally the patch fixes some ppc regressions for altivec and vmx.   
It required to modify address transformations and generations of reloads 
involving the secondary memory.  The problem imho is in a bad practice 
in rs6000 machine descriptions when there are contradictory requirements 
of predicate and constraints.  For example,

(define_insn "*altivec_mov<mode>"
   [(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,*o,*r,*r,v,v")
         (match_operand:VM2 1 "input_operand" "v,Z,v,r,o,r,j,W"))]
   "VECTOR_MEM_ALTIVEC_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
        || register_operand (operands[1], <MODE>mode))"

Predicates requires only base or base+index addressing and constraints 
'o' permits offsetable addressing.

The patch was successfully bootstrapped on x86/x86-64 and power7 and was 
committed as r181117.

2011-11-07  Vladimir Makarov <vmakarov@redhat.com>

     * lra-int.h (lra_coalesce, lra_spill): Change the prototype.
     (lra_need_for_spills_p): New prototype.

     * lra.c (lra): Move coalesce after assignment.  Call
     lra_need_for_spills_p before lra_create_live_ranges.  Don't check
     return value of lra_spill.

     * lra-spills.c (spill_pseudos, lra_spill): Don't return value.
     (lra_need_for_spills_p): New function.
     (lra_hard_reg_substitution): Use max_reg_num instead of regs_num.

     * lra-coalesce.c (lra_coalesce): Move side_effects call lower.
     Check restore_regno.  Process only insns containing coalesced
     pseudos for pseudo substitution.  Return flag that some moves were
     coalesced.

     * lra-constraints.c (get_final_hard_regno): Move up.
     (get_op_class, emit_secondary_memory_move): New functions.
     (check_and_process_move): Add code for quick validity check base
     on move cost.  Use emit_secondary_memory_move.
     (process_address): Don't use transformation base + disp => base +
     new index.
     (curr_reload_insn_check, reload_insn_check, reload_insn): Rename
     correspondingly to curr_usage_insns_check, usage_insns_check, and
     usage_insns.
     (substitute_pseudo): New function.
     (inherit_reload_reg): Change prototype.  Add code to reject
     generated reload inheritance insns.  Change the generated
     inheritance code for permitting not only move insns in the
     inheritance.  Use substitute_pseudo.
     (live_pseudos): New bitmap.
     (update_ebb_live_info): New function.
     (struct to_inherit): New.
     (to_inherit): New array.
     (to_inherit_num): New static variable.
     (add_to_inherit): New function.
     (inherit_in_ebb): Add code for inheritance in non-reload
     functions.  Process debug insns too.
     (lra_inheritance): Initialize/finalize check_only_pseudos and
     live_pseudos.  Call update_ebb_live_info.
     (remove_inheritance_pseudos): Process debug insns too.  Add
     special cases to undo the inheritance transformations.

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