[RFC] Fix full memory barrier on SPARC-V8

[David Miller]

From: Geert Bosch <bosch@adacore.com>
Date: Mon, 27 Jun 2011 22:21:47 -0400

> On Jun 27, 2011, at 19:53, David Miller wrote:
> 
>> Adding a ldstub here is going to be really expensive, on UltraSparc
>> that can be 36+ cycles even on a cache hit.
> 
> Yes, synchronization in multi-CPU systems is expensive.
> If it's really cheap, you're probably doing something wrong.

First, I fundamentally disagree with this assertion.  The reason
proper memory barriers exist is so that you don't need nonsense like
these proposed atomics to get proper memory operation ordering.

A proper membar on your v9 test system is orders of magnitude cheaper
than this stbar+ldstub business.

You then go on to speak about LEON, does LEON implement PSO?