[PATCH][RFC][2/2] Bitfield lowering

Richard Guenther rguenther@suse.de
Mon Jun 27 22:08:00 GMT 2011


On Mon, 27 Jun 2011, Richard Henderson wrote:

> On 06/23/2011 02:49 AM, Richard Guenther wrote:
> > So, do you know of a target that can do insv with a memory
> > target?  I would expect extv on memory to be easily doable.
> 
> Depends on what you mean by that.  INSV is the traditional
> md pattern that performs unaligned stores.  So, many targets
> can handle a memory destination of some sort

Hm, the code that seems to deal with HAVE_insv seems to be indeed
generic (via store_bit_field).  But that would only mean that
lowering bitfields should be considered in the context of lowering
unaligned accesses (on targets that require that).

> Many many less would handle memory if we completed the 
> transition of unaligned memory load/store to movmisalign.
> But at present movmisalign is only defined for vector modes.

I think the ideal point would be when movmisaling would only
expand to native unaligned load single instructions.  Multiple
instruction sequences should be exposed at a (lowered) gimple
level.

Now the question is if there is a useful intermediate step
to that ideal result.  That is, if we transition memory
BIT_FIELD_REFs to a mode-size load and a register bit extract
we can for the purpose of expansion easily present that as
bit extract on a memory operand.  Similar for a store from
a BIT_FIELD_COMPOSE_EXPR.

So that definitely points in favor of using BIT_FIELD_*
for the lowering instead of decomposing those to shifts
and bitwise operations.

Richard.



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