PATCH [11/n]: Prepare x32: PR rtl-optimization/48155: Reload doesn't handle subreg properly

[H.J. Lu]

On Mon, Jun 27, 2011 at 7:52 AM, Ulrich Weigand <uweigand@de.ibm.com> wrote:
> H.J. Lu wrote:
>
>> Given input:
>>
>> (plus:SI (subreg:SI (plus:DI (reg/f:DI 7 sp)
>>             (const_int 16 [0x10])) 0)
>>     (const_int -1 [0xffffffffffffffff]))
>
> Once again, this seems weird as legitimate address ...  If this really
> can occur validly, there'll probably need to be an insn+splitter and/or
> a secondard reload provided by the back-end to handle it.

This is the valid memory address for any instructions which
take a memory operand under x32.  How will insn+splitter and/or
a secondard reload help x32 here? Do I implement such a thing for
all instructions which take a memory operand?

>> reloads tries to add
>>
>> (subreg:SI (plus:DI (reg/f:DI 7 sp)
>>         (const_int 16 [0x10])) 0)
>>
>> to
>>
>> (reg:SI 1 dx)
>
> And what happens then?  If the only problem is that this is then
> rejected by the back-end, I don't think we need to change anything
> in gen_reload ...
>
> With your change below, it seems you're just falling through to
> the generic gen_rtx_SET case, right?   How does this help?
>

I added ix86_simplify_base_disp to i386.c to handle such cases.
It translates

(set (reg:SI 40 r11)
        (plus:SI (plus:SI (mult:SI (reg:SI 1 dx)
                                   (const_int 8))
                          (subreg:SI (plus:DI (reg/f:DI 7 sp)
                                              (const_int CONST1)) 0))
                 (const_int CONST2)))

  into

   (set (reg:SI 40 r11)
        (plus:SI (plus:SI (mult:SI (reg:SI 1 dx)
                                   (const_int 8))
                          (reg/f:SI 7 sp))
                 (const_int [CONST1 + CONST2])))

   It also translates

   (plus:DI (zero_extend:DI (plus:SI (plus:SI (reg:SI 4 si [70])
                                              (reg:SI 2 cx [86]))
                                     (const_int CONST1)))
            (const_int CONST2))

   into

   (plus:DI (zero_extend:DI (plus:SI (reg:SI 4 si [70])
                                     (reg:SI 2 cx [86]))
            (const_int [CONST1 + CONST2])))

  It also translates

   (plus:SI (plus:SI (plus:SI (reg:SI 4 si [70])
                              (reg:SI 2 cx [86]))
                     (symbol_ref:SI ("A.193.2210")))
            (const_int CONST))

   into

   (plus:SI (plus:SI (reg:SI 4 si [70])
                     (reg:SI 2 cx [86]))
            (const (plus:SI (symbol_ref:SI ("A.193.2210"))
                            (const_int CONST))))

   It aslo translates

   (set (reg:SI 40 r11)
        (plus:SI (plus:SI (reg:SI 1 dx)
                          (subreg:SI (plus:DI (reg/f:DI 7 sp)
                                              (const_int CONST1)) 0))
                 (const_int CONST2)))

   into

   (set (reg:SI 40 r11)
        (plus:SI (plus:SI (reg:SI 1 dx)
                          (reg/f:SI 7 sp))
                 (const_int [CONST1 + CONST2])))


-- 
H.J.