[PATCH][RFC][1/2] Bitfield lowering, add BIT_FIELD_EXPR
William J. Schmidt
wschmidt@linux.vnet.ibm.com
Sun Jun 19 23:45:00 GMT 2011
On Thu, 2011-06-16 at 13:35 +0200, Richard Guenther wrote:
> This is a (possible) pre-requesite for the bitfield lowering patch,
> taken from the old mem-ref branch. It introduces BIT_FIELD_EXPR
> which can be used to do bitfield composition.
> BIT_FIELD_EXPR <a, b, C1, C2> is equivalent to computing
> a & ~((1 << C1 - 1) << C2) | ((b << C2) & (1 << C1 = 1)), thus
> inserting b of width C1 at the bitfield position C2 in a, returning
> the new value. This allows translating
> BIT_FIELD_REF <a, C1, C2> = b;
> to
> a = BIT_FIELD_EXPR <a, b, C1, C2>;
> which avoids partial definitions of a (thus, BIT_FIELD_EXPR is
> similar to COMPLEX_EXPR). BIT_FIELD_EXPR is supposed to work
> on registers only.
>
> Comments welcome, esp. on how to avoid introducing quaternary
> RHS on gimple stmts (or using a GIMPLE_SINGLE_RHS as the patch does).
>
At the risk of being obvious...it seems you could easily combine C1 and
C2 into a single "bitfield descriptor" TREE_INT_CST operand by using
both the high and low portions of the constant. Accessor macros could
be used to hide the slight hackishness of the solution. I didn't see
anything in either patch where this would look particularly ugly.
Storing operands differently than in BIT_FIELD_REF isn't ideal, but
perhaps it's better than a quaternary RHS. /shrug
Bill
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