[patch, ARM] PR47246, VFP index range on Thumb-2

[Chung-Lin Tang]

On 2011/1/25 下午 03:03, Chung-Lin Tang wrote:
> Hi,
> This fixes a condition I overlooked in a prior patch. The allowed
> Thumb-2 load/store index range for core registers is -256--4096
> exclusive, while the coprocessor range is still -1024--1024 like ARM
> mode. The valid intersection is then -256--1024.
> 
> This actually relates to the problem of having different valid memory
> addresses for the same machine mode when load/storing to different
> register classes (here SF/DF modes stored in both GPR and FPU regs, with
> differing index ranges), which does not seem to be an easy problem
> within GCC.
> 
> So here's the conservative patch, again tested without regressions.  It
> corrects other coprocessor cases (FPA, Maverick) together, which should
> be correct (not that I've seen Thumb-2 implementations with them)
> 
> Okay for trunk?

Forgot to attach patch :P
Here it is:

2011-01-25  Chung-Lin Tang  <cltang@codesourcery.com>

        * config/arm/arm.c (thumb2_legitimate_index_p): Change the
        lower bound of the allowed Thumb-2 coprocessor load/store
        index range to -256. Add explaining comment.

-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: t2vfp.diff
URL: <http://gcc.gnu.org/pipermail/gcc-patches/attachments/20110125/bac52352/attachment.ksh>