[ia64, rfa] vector pattern improvements

Steve Ellcey sje@cup.hp.com
Thu Jan 6 18:38:00 GMT 2011


Richard,

I am trying to fix the new IA64 vector instructions you added so they
work on HP-UX (big-endian) and would like to get some feedback on
whether or not I am going about it in the correct way.  The attached
patch fixes some (but not most) of the gcc.dg/vect failures I am seeing
and I would like to verify that the vect_extract* instructions I am 
changing are the best place to address the big-endian/little-endian
differences.

At first I tried changing the vec_pack to call gen_vec_extract* with
different options but now I think leaving the vec_pack* instructions
alone and changing vec_extract* is better, but I am not sure if one
or the other of these locations is considered the 'right' place to
address endian issues.

Can you offer any advise?

Steve Ellcey
sje@cup.hp.com


Index: config/ia64/vect.md
===================================================================
--- config/ia64/vect.md	(revision 168534)
+++ config/ia64/vect.md	(working copy)
@@ -1,5 +1,5 @@
 ;; IA-64 machine description for vector operations.
-;; Copyright (C) 2004, 2005, 2007, 2010 Free Software Foundation, Inc.
+;; Copyright (C) 2004, 2005, 2007 Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
 ;;
@@ -857,7 +857,10 @@ (define_expand "vec_extract_evenv8qi"
   ""
 {
   rtx temp = gen_reg_rtx (V8QImode);
-  emit_insn (gen_mix1_r (temp, operands[1], operands[2]));
+  if (TARGET_BIG_ENDIAN)
+    emit_insn (gen_mix1_r (temp, operands[2], operands[1]));
+  else
+    emit_insn (gen_mix1_r (temp, operands[1], operands[2]));
   emit_insn (gen_mux1_alt (operands[0], temp));
   DONE;
 })
@@ -869,7 +872,10 @@ (define_expand "vec_extract_oddv8qi"
   ""
 {
   rtx temp = gen_reg_rtx (V8QImode);
-  emit_insn (gen_mix1_l (temp, operands[1], operands[2]));
+  if (TARGET_BIG_ENDIAN)
+    emit_insn (gen_mix1_l (temp, operands[2], operands[1]));
+  else
+    emit_insn (gen_mix1_l (temp, operands[1], operands[2]));
   emit_insn (gen_mux1_alt (operands[0], temp));
   DONE;
 })
@@ -967,7 +973,10 @@ (define_expand "vec_extract_evenv4hi"
   ""
 {
   rtx temp = gen_reg_rtx (V4HImode);
-  emit_insn (gen_mix2_r (temp, operands[1], operands[2]));
+  if (TARGET_BIG_ENDIAN)
+    emit_insn (gen_mix2_r (temp, operands[2], operands[1]));
+  else
+    emit_insn (gen_mix2_r (temp, operands[1], operands[2]));
   emit_insn (gen_vec_extract_evenodd_helper (operands[0], temp));
   DONE;
 })
@@ -979,7 +988,10 @@ (define_expand "vec_extract_oddv4hi"
   ""
 {
   rtx temp = gen_reg_rtx (V4HImode);
-  emit_insn (gen_mix2_l (temp, operands[1], operands[2]));
+  if (TARGET_BIG_ENDIAN)
+    emit_insn (gen_mix2_l (temp, operands[2], operands[1]));
+  else
+    emit_insn (gen_mix2_l (temp, operands[1], operands[2]));
   emit_insn (gen_vec_extract_evenodd_helper (operands[0], temp));
   DONE;
 })
@@ -1024,8 +1036,12 @@ (define_expand "vec_extract_evenv2si"
    (match_operand:V2SI 2 "gr_register_operand" "")]
   ""
 {
-  emit_insn (gen_vec_interleave_lowv2si (operands[0], operands[1],
-					 operands[2]));
+  if (TARGET_BIG_ENDIAN)
+    emit_insn (gen_vec_interleave_lowv2si (operands[0], operands[2],
+					   operands[1]));
+  else
+    emit_insn (gen_vec_interleave_lowv2si (operands[0], operands[1],
+					   operands[2]));
   DONE;
 })
 
@@ -1035,8 +1051,12 @@ (define_expand "vec_extract_oddv2si"
    (match_operand:V2SI 2 "gr_register_operand" "")]
   ""
 {
-  emit_insn (gen_vec_interleave_highv2si (operands[0], operands[1],
-					  operands[2]));
+  if (TARGET_BIG_ENDIAN)
+    emit_insn (gen_vec_interleave_lowv2si (operands[0], operands[2],
+					   operands[1]));
+  else
+    emit_insn (gen_vec_interleave_highv2si (operands[0], operands[1],
+					    operands[2]));
   DONE;
 })
 
@@ -1399,8 +1419,12 @@ (define_expand "vec_extract_evenv2sf"
    (match_operand:V2SF 2 "gr_register_operand" "")]
   ""
 {
-  emit_insn (gen_vec_interleave_lowv2sf (operands[0], operands[1],
-					 operands[2]));
+  if (TARGET_BIG_ENDIAN)
+    emit_insn (gen_vec_interleave_highv2sf (operands[0], operands[2],
+					   operands[1]));
+  else
+    emit_insn (gen_vec_interleave_lowv2sf (operands[0], operands[1],
+					   operands[2]));
   DONE;
 })
 
@@ -1410,8 +1434,12 @@ (define_expand "vec_extract_oddv2sf"
    (match_operand:V2SF 2 "gr_register_operand" "")]
   ""
 {
-  emit_insn (gen_vec_interleave_highv2sf (operands[0], operands[1],
-					  operands[2]));
+  if (TARGET_BIG_ENDIAN)
+    emit_insn (gen_vec_interleave_lowv2sf (operands[0], operands[2],
+					    operands[1]));
+  else
+    emit_insn (gen_vec_interleave_highv2sf (operands[0], operands[1],
+					    operands[2]));
   DONE;
 })
 



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