RFA: MN10300: Add AM34 target and scheduling

[Nick Clifton]

Hi Jeff,

> I'd really like to see some further analysis of the circumstances that
> lead to the spill failure on the mn103.

Fair enough - I was being lazy by not investigating further.  Taking 
20021120-3.c as my test case, here is what happens.  Before the first 
scheduling pass we have:

(insn  3 (set (reg:SI 64 [ x ]) (reg:SI d1 [ x ]))

(insn  4 (set (reg:SI 65 [ y ]) (mem/c/i:SI (plus:SI (reg:SI ap) 
(const_int 12))

(insn  9 (set (reg:SI 68)  (udiv:SI (reg/v:SI 64 [ x ]) (reg/v:SI 65 [ y 
])))
          (set (reg:SI 69)  (umod:SI (reg/v:SI 64 [ x ]) (reg/v:SI 65 [ 
y ])))

(insn 10 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12)) (reg:SI 68))

(insn 12 (set (reg:SI d1)  (symbol_ref:SI ("*.LC0")

(call 13 (set (reg:SI d0)  (call (mem:QI (symbol_ref:SI ("sprintf")))))


After the scheduling pass this becomes:


(insn  3 (set (reg:SI 64 [ x ])  (reg:SI d1 [ x ]))

(insn  4 (set (reg:SI 65 [ y ])  (mem:SI (plus:SI (reg:SI ap) (const_int 
12))

(insn 12 (set (reg:SI d1)  (symbol_ref:SI ("*.LC0")))

(insn  9 (set (reg:SI 68)  (udiv:SI (reg:SI 64 [ x ]) (reg:SI 65 [ y ])))
          (set (reg:SI 69)  (umod:SI (reg:SI 64 [ x ]) (reg:SI 65 [ y ])))

(insn 10 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12)) (reg:SI 68))

(call 13 (set (reg:SI d0)  (call (mem:QI (symbol_ref:SI ("sprintf")


Note how insn 12 has been moved before insn 9.  This means that both d0 
and d1 are now live at insn 9, and hence there are insufficient 'd' 
registers to spill.

I am not sure how to correct this though.  Any suggestions ?

Cheers
   Nick