[patch 1/3] AMD bdver2 processors - BMI

Quentin Neill quentin.neill.gnu@gmail.com
Thu Oct 21 00:46:00 GMT 2010


On Mon, Oct 18, 2010 at 6:01 PM, Quentin Neill
<quentin.neill.gnu@gmail.com> wrote:
> On Mon, Oct 18, 2010 at 2:25 PM, Richard Henderson <rth@redhat.com> wrote:
>> On 10/15/2010 11:45 AM, Quentin Neill wrote:
>>> The public specifications for BMI and TBM are in progress (they are
>>> today available under NDA).  They will appear in one of the AMD64
>>> Architecture Programmer's Manual Volumes 3-6.   I can post the
>>> mnemonics definitions if needed.
>>
>> Please do.  From the names, it *seems* like most of the BMI insns
>> should be represented with normal RTL and not via unspecs.  Which
>> also begs the question of why there would need to be builtins for
>> some of them.
>> r~
>
> Hi Richard,
>
> You might have access to the full TBM/BMI spec via our NDA website:
> https://nda.amd.com/dds/user/doc/12810D23584.PDF
>
> I will reply to the list with the mnemonics (in review).
>
> We decided to go with unspecs to get them into 4.6 before it closes,
> in part because I am new to the backend.  I looked at the RTL operands
> and it didn't seem trivial, but I agree that most of these
> instructions are just compound bit manipulations ( and, or,
> ones-compl, addition, subtraction).
>
> --
> Quentin

Mnemonics/short description for BMI instructions below
-- 
Quentin


# BMI Instructions
# Descriptions are subject to change

#ANDN dest, src1, src2 - Logical And-Not: bitwise and of src2 with
one's complement of src1 into dest
ANDN reg32, reg32, reg/mem32 C4 RXB.02 0.src1.0.00 F2 /r
ANDN reg64, reg64, reg/mem64 C4 RXB.02 1.src1.0.00 F2 /r

#BEXTR dest, src, cntl - Bit Field Extract: extract src[S+L-1:S] to
dest, where L=cntl[15:8] and S=cntl[7:0]
BEXTR reg32, reg/mem32, reg32 C4 RXB.02 0.cntl.0.00 F7 /r
BEXTR reg64, reg/mem64, reg64 C4 RXB.02 1.cntl.0.00 F7 /r

#BLSI dest, src - Isolate Lowest Set Bit (X & -X): extract LSB set to
1 from src to dest
BLSI reg32, reg/mem32 C4 RXB.02 0.dest.0.00 F3 /3
BLSI reg64, reg/mem64 C4 RXB.02 1.dest.0.00 F3 /3

#BLSMSK dest, src - Mask From Lowest Set Bit (X^(X-1)): write mask of
1s in dest[L:0] to dest, where L is LSB in src
BLSMSK reg32, reg/mem32 C4 RXB.02 0.dest.0.00 F3 /2
BLSMSK reg64, reg/mem64 C4 RXB.02 1.dest.0.00 F3 /2

#BLSR dest, src - Reset Lowest Set Bit (X&(X-1)): clear LSB in src and
write to dest
BLSR reg32, reg/mem32 C4 RXB.02 0.dest.0.00 F3 /1
BLSR reg64, reg/mem64 C4 RXB.02 1.dest.0.00 F3 /1

#note that LZCNT is an ABM instruction, it's listed here for completeness
#LZNT dest, src - Count Leading Zeros : Count number of leading zeros in src
#LZCNT reg16, reg/mem16 F3 0F BD /r
#LZCNT reg32, reg/mem32 F3 0F BD /r
#LZCNT reg64, reg/mem64 F3 0F BD /r

#TZNT dest, src - Count Trailing Zeros: Count number of trailing zeros in src
TZCNT reg16, reg/mem16 F3 0F BC /r
TZCNT reg32, reg/mem32 F3 0F BC /r
TZCNT reg64, reg/mem64 F3 0F BC /r



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