[Patch : H8300] Minor bug fix for bit instructions
Kaushik Phatak
Kaushik.Phatak@kpitcummins.com
Mon Nov 8 09:06:00 GMT 2010
Hi Jeff,
Thanks for your detailed review.
Please find below an updated patch with the suggested changes,
- Changelog more explicit
- formatting corrections
- Testcase added to gcc.dg
Please let me know if these are OK.
Thanks,
Kaushik Phatak
www.kpitgnutools.com
Changelog:
2010-11-08 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
* config/h8300/h8300.md (define_split) : Add condition for
"and with single_zero" splitter to handle 16-bit const operands.
* config/h8300/h8300.md (define_split) : Add condition for
"ior with single_one" splitter to handle 16-bit const operands.
* config/h8300/h8300.md (define_split) : Add condition for
"xor with single_one" splitter to handle 16-bit const operands.
diff -upr trunk.orig/gcc/config/h8300/h8300.md trunk/gcc/config/h8300/h8300.md
--- trunk.orig/gcc/config/h8300/h8300.md 2010-08-26 20:55:19.000000000 +0530
+++ trunk/gcc/config/h8300/h8300.md 2010-10-28 19:57:14.000000000 +0530
@@ -1781,8 +1781,17 @@
(and:QI (match_dup 1)
(match_dup 2)))]
{
- operands[0] = adjust_address (operands[0], QImode, 1);
- operands[1] = adjust_address (operands[1], QImode, 1);
+ if (abs (INTVAL (operands[2])) > 0xFF)
+ {
+ operands[0] = adjust_address (operands[0], QImode, 0);
+ operands[1] = adjust_address (operands[1], QImode, 0);
+ operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
+ }
+ else
+ {
+ operands[0] = adjust_address (operands[0], QImode, 1);
+ operands[1] = adjust_address (operands[1], QImode, 1);
+ }
})
(define_insn "bclrhi_msx"
@@ -1916,8 +1925,17 @@
(ior:QI (match_dup 1)
(match_dup 2)))]
{
- operands[0] = adjust_address (operands[0], QImode, 1);
- operands[1] = adjust_address (operands[1], QImode, 1);
+ if (abs (INTVAL (operands[2])) > 0xFF)
+ {
+ operands[0] = adjust_address (operands[0], QImode, 0);
+ operands[1] = adjust_address (operands[1], QImode, 0);
+ operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
+ }
+ else
+ {
+ operands[0] = adjust_address (operands[0], QImode, 1);
+ operands[1] = adjust_address (operands[1], QImode, 1);
+ }
})
(define_insn "bsethi_msx"
@@ -1982,8 +2000,17 @@
(xor:QI (match_dup 1)
(match_dup 2)))]
{
- operands[0] = adjust_address (operands[0], QImode, 1);
- operands[1] = adjust_address (operands[1], QImode, 1);
+ if (abs (INTVAL (operands[2])) > 0xFF)
+ {
+ operands[0] = adjust_address (operands[0], QImode, 0);
+ operands[1] = adjust_address (operands[1], QImode, 0);
+ operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
+ }
+ else
+ {
+ operands[0] = adjust_address (operands[0], QImode, 1);
+ operands[1] = adjust_address (operands[1], QImode, 1);
+ }
})
(define_insn "bnothi_msx"
diff -upN trunk.orig/gcc/testsuite/gcc.dg/h8300-bit-insn-ice.c trunk/gcc/testsuite/gcc.dg/h8300-bit-insn-ice.c
--- trunk.orig/gcc/testsuite/gcc.dg/h8300-bit-insn-ice.c 1970-01-01 05:30:00.000000000 +0530
+++ trunk/gcc/testsuite/gcc.dg/h8300-bit-insn-ice.c 2010-11-08 11:43:23.000000000 +0530
@@ -0,0 +1,39 @@
+/* { dg-skip-if "" { "h8300*-*-*" } "*" "-msx*" } */
+/* ICE for bit instruction generation using 16-bit const */
+
+__extension__ struct st_mstp
+{
+ union
+ {
+ unsigned short WORD;
+ struct
+ {
+ unsigned char ACSE:1;
+ unsigned char _EXDMAC:1;
+ unsigned char _DMAC:1;
+ unsigned char _DTC:1;
+ unsigned char:2;
+ unsigned char _TMR23:1;
+ unsigned char _TMR01:1;
+ unsigned char:2;
+ unsigned char _DA:1;
+ unsigned char:1;
+ unsigned char _AD:1;
+ unsigned char:1;
+ unsigned char _TPUU:1;
+ unsigned char _TPUL:1;
+ } BIT;
+ } CRA;
+};
+#define MSTP (*(volatile struct st_mstp *)0xFFFDC8)
+#define MSTPA_EXDMA 0x4000
+#define MSTPA_AND 0xFEFF
+
+int
+main ()
+{
+ MSTP.CRA.WORD |= MSTPA_EXDMA;
+ MSTP.CRA.WORD ^= MSTPA_EXDMA;
+ MSTP.CRA.WORD &= MSTPA_AND;
+ return 0;
+}
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