PATCH: Mention x86 configure changes for gcc 4.5.0

[Sebastian Pop]

Hi,

2010/2/26 Uros Bizjak <ubizjak@gmail.com>:
> At least <x86intrin.h> should be mentioned. There is also whole lot of
> contributed code with user-visible compile flag that definitely deserves a
> line or two in changes.html (H.J and Sebastian - can you please add
> something about these?):
>
> mfma
> Target Report Mask(ISA_FMA) Var(ix86_isa_flags) VarExists
> Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in
> functions and code generation
>
> msse4a
> Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) VarExists Save
> Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code
> generation
>
> mfma4
> Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) VarExists Save
> Support FMA4 built-in functions and code generation
>
> mxop
> Target Report Mask(ISA_XOP) Var(ix86_isa_flags) VarExists Save
> Support XOP built-in functions and code generation
>
> mlwp
> Target Report Mask(ISA_LWP) Var(ix86_isa_flags) VarExists Save
> Support LWP built-in functions and code generation
>
> mabm
> Target Report Mask(ISA_ABM) Var(ix86_isa_flags) VarExists Save
> Support code generation of Advanced Bit Manipulation (ABM) instructions.
>
> mpopcnt
> Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) VarExists Save
> Support code generation of popcnt instruction.
>
> mmovbe
> Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) VarExists Save
> Support code generation of movbe instruction.
>
> mcrc32
> Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) VarExists Save
> Support code generation of crc32 instruction.
>
> maes
> Target Report Mask(ISA_AES) Var(ix86_isa_flags) VarExists Save
> Support AES built-in functions and code generation
>
> mpclmul
> Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) VarExists Save
> Support PCLMUL built-in functions and code generation
>
> Uros.
>

Here is the patch for AMD's contributions to gcc-4.5.  Ok to commit?

Thanks,
Sebastian Pop
--
AMD / Open Source Compiler Engineering / GNU Tools



*** changes.html	31 Mar 2010 15:08:50 -0500	1.77
--- changes.html	31 Mar 2010 16:09:46 -0500	
***************
*** 596,603 ****
      </li>
      <li>SSE math now can be enabled by default at configure time with the
      new <code>--with-fpmath=sse</code> option.</li>
!     <li>There is a new intrinic header file, <x86intrin.h>. It
      should be included before using any IA-32/x86-64 intrinsics.</li>
    </ul>

  <h3>M68K/ColdFire</h3>
--- 596,613 ----
      </li>
      <li>SSE math now can be enabled by default at configure time with the
      new <code>--with-fpmath=sse</code> option.</li>
!     <li>There is a new intrinsic header file, <x86intrin.h>. It
      should be included before using any IA-32/x86-64 intrinsics.</li>
+     <li>Support for the XOP, FMA4, and LWP instruction sets for the AMD
+     Orochi processors are now available with
+     the <code>-mxop</code>, <code>-mfma4</code>,
+     and <code>-mlwp</code> flags.</li>
+     <li> The <code>-mabm</code> flag enables GCC to use
+     the <code>popcnt</code> and <code>lzcnt</code> instructions on AMD
+     processors.</li>
+     <li> The <code>-mpopcnt</code> flag enables GCC to use
+     the <code>popcnt</code> instructions on both AMD and Intel
+     processors.</li>
    </ul>

  <h3>M68K/ColdFire</h3>